Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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TL;DR: Experimental results show that using the proposed method, both EM reliability and power integrity can be met, while the additional metal area used is significantly reduced.
Abstract: Electromigration (EM) has become a major power grid reliability problem in VLSI. In this paper, we first demonstrate that EM reliability analysis of a power grid can be converted to analyzing EM reliability of the grid vias. We develop a model for calculating EM lifetime of via-arrays and observe that making power grid EM-immortal carries a huge metal area overhead and possibly makes routing of both power and signal networks too difficult to complete. We propose a method for trading off power grid integrity and reliability to minimize the total metal area overhead needed to achieve the desired grid life time under power integrity constraints. Experimental results show that using our method, both EM reliability and power integrity can be met, while the additional metal area used is significantly reduced.
33 citations
TL;DR: In this article, the authors developed the method of broadband Green's function with low-wavenumber extraction (BBGFL) for arbitrary shaped waveguide for broadband simulations of vias in printed circuit boards (PCB).
Abstract: In this paper we developed the method of broadband Green's function with low wavenumber extraction (BBGFL) for arbitrary shaped waveguide. The case of Neumann boundary condition is treated. The BBGFL has the advantage that when using it to solve boundary value problems in a waveguide, the boundary conditions have been satisfied already. The broadband Green's function is expressed in modal expansion of modes that are frequency independent. To accelerate the convergence of the Green's function, a low wavenumber extraction is performed. The singularity of the Green's function is also extracted by such low wavenumber extraction. Numerical results show that BBGLF and direct MoM are in good agreement. We next illustrate the application of BBGFL for broadband simulations of vias in printed circuit boards (PCB) by combining with the method of Foldy-Lax multiple scattering equation. The results show that BBGFL are in good agreement with MoM and HFSS. It is also shown that BBGFL is many times faster than direct MoM and HFSS. The computational efficiency in broadband simulations makes this technique useful for fast computer-aided design (CAD). The effects of waveguide or cavity structures are critical for the electrical performance of electronic devices and components in signal integrity (SI), power integrity (PI), electromagnetic interference (EMI), and electromagnetic compatibility (EMC). Harmful electromagnetic signal noises or interferences are often generated and amplified at the resonant frequencies of the waveguide or cavity structures. The issues deteriorate when the electronic devices or computer systems operate at higher frequency or faster speed. In printed circuited boards (PCBs), two adjacent power/ground planes form a waveguide/cavity structure. The propagating modes satisfy the PMC (Neumann boundary conditions) at the edges of PCB power/ground plane structures. The power/ground plane structures are the key root causes in SI/PI and EMI/EMC problems. Vias are used for vertical interconnects for multilayer PCBs. At frequencies near the resonant frequencies, the propagating electromagnetic waves excite resonant modes, that result in strong edge radiations. These cause EMI/EMC problems. The switching noises induced by voltage regulator module (VRM) generate voltage fluctuations and lead to PI problems. The high frequency power noise can also couple into signal vias and cause SI/PI coupling issues. Therefore, the modeling of PCB cavity with vias is critical in practical designs and applications of high speed PCBs and packages. Fast and accurate modeling technique is desired for broadband simulations in electronic design and application. The finiteness of the parallel power/ground planes make them waveguide/cavity structures. The power/ground planes are also of arbitrary shape. Commercial tools such as HFSS provide solutions for the analysis of the via-cavity coupling problem. The tools require large CPU and memory and are not suited for broadband analysis. The physical problem is that of TM modes in a cavity with PMC boundary conditions on the side walls. Various methods have been used for waveguide
32 citations
01 Jul 2018
TL;DR: This article consists only of a collection of slides from the author's conference presentation.
Abstract: This article consists only of a collection of slides from the author's conference presentation.
31 citations
07 Apr 2011
TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.
Abstract: Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.
31 citations
TL;DR: In this article, a methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented.
Abstract: A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.
31 citations