Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

High bandwidth application with Wide I/O memory on 2.5D-IC silicon interposer

Abstract: A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.

A system-level equivalent circuit method for the electrical performance modeling of electronic packages

Abstract: In this paper, we propose a system-level field-circuit method for the signal integrity and power integrity simulation of power distribution networks inside the electronic packages. The electromagnetic field inside the power distribution network is expressed in the modal field distribution. The modal field is then decomposed into the parallel plate mode and transmission mode, which are related to the power-ground planes and signal traces respectively. Integral equations are created for these two modes. Through the discretization of the integral equations, network ports are defined between the power/ground planes and signal traces. In this way, their equivalent networks are extracted through the moments method solution of the integral equations. Finally, these two equivalent networks are combined together with the equivalent circuit of the through-hole via to provide the whole circuit model of the power distribution network. Through numerical examples, the accuracy and efficiency of the proposed method are verified.

Embedded passive components for improved power plane decoupling

Abstract: In this paper, a detailed power integrity study is described that compares the behavior of surface-mount devices and embedded components for power decoupling. Through measurements and simulations, it is found that when the layer count of the board is low, there is no significant difference between both technologies. When the number of layers increases, the short connection for the embedded components is clearly superior to the surface-mount capacitor. The resonance frequencies for the embedded capacitor do not change significantly with the increased layer count. The case with the surface-mount capacitor however, shows a large increase in parasitic inductance due to the long vias through the board.

Modeling and analysis of TSV noise coupling and suppression methods for 20nm node and beyond

Abstract: With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper, the noise coupling effect between TSVs and corresponding suppression methods were modeled and analyzed. Effect of variations of structural parameters on noise coupling are investigated and results are explained based on specifications of advanced technology node. In order to alleviate noise effect under fine pitch scenario, different noise suppression methods are discussed and compared. The guard-ring didn't demonstrate much noise reduction over the whole frequency spectrum, with slightly better performance within the low frequency range. The buried oxide layer of SOI technology also showed little suppression effect in blocking substrate noise. However, the TSV array scheme is significantly effective in noise suppression over the whole frequency spectrum.

New structure of composite power plane using spiral ebg and external magnetic material for ssn suppression

Abstract: A new structure of composite power plane with a spiral electromagnetic bandgap (EBG) and an external magnetic material is proposed for the suppression of simultaneous switching noise (SSN) in the mixed-signal systems. The new structure proposed in the present research is designed with an external magnetic material and the spiral EBG structure. The new structure is relatively simple to fabricate and cost efiective because the external magnetic material is partially placed on the top of perforated spiral-bridged EBG plane. The EBG bandgap is shifted to lower frequencies by the real part of the permeability (" 0 ), and the power plane Q-factor is also decreased by the imaginary part of the permeability (" 00 ) associated with the magnetic loss. It is expected the reduction of a circuit size and an improvement of the power integrity with the mixed-signal systems in the given new structure.