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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings ArticleDOI
01 Oct 2020
TL;DR: In this article, the authors conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time.
Abstract: The optimal selection of an interposer substrate is important in 2.5D systems, because its physical, material and electrical characteristics govern the overall system performance, reliability and cost. Several materials have been proposed that offer various tradeoffs including silicon, organic, glass and etc. In this paper, we conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time. We also investigate tradeoffs in power, performance and area (PPA), signal integrity (SI) and power integrity (PI) depending on the interposer technologies. Through our flow, we generate a large-scale benchmark architecture with commercial-grade GDS layouts of interposer and chiplets using two different interposer substrates. Then, we model transmission lines and power delivery network (PDN) of each 2.5D IC design. Finally, we perform PPA analysis, SI and PI on both 2.5D IC designs to observe the quantitative tradeoffs between two designs. Our experiment shows that silicon interposer-based design has 10.46% less power, 0.25× smaller area and 0.57× shorter average wirelength compared to LCP interposer-based design. However, LCP-based design has 0.59× smaller PDN DC impedance and 0.75× shorter worst delay of interposer wire while maintaining the power delivery efficiency. Lastly, our cost analysis of 2.5D IC design indicates that the overall cost of organic LCP technology, if both the chiplets and their interposer costs are combined, is 2.69× higher than the silicon even the cost of LCP interposer is 1.91% of silicon interposer. This indicates that LCP technology is prohibitive unless the interconnect and bump dimensions are dramatically reduced.

3 citations

Proceedings ArticleDOI
17 May 2016
TL;DR: In this paper, a transient simulation analysis for printed circuit board (PCB) power distribution network (PDN) by using physics-based circuit model is proposed, where PCB PDN is divided into different blocks.
Abstract: A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.

3 citations

Proceedings ArticleDOI
14 Oct 2019
TL;DR: In this article, the analysis of through silicon via (TSV) with embedded capacitor for impedance tuning to improve the power integrity (PI) performance of application specific integrated circuit-highbandwidth memory (ASIC-HBM) system is presented.
Abstract: This paper presents the analysis of through silicon via (TSV) with embedded capacitor for impedance tuning to improve the power integrity (PI) performance of Application-Specific Integrated Circuit – High Bandwidth Memory (ASIC-HBM) system. The crosstalk due to TSV with embedded capacitor (TSV-Cap) to signal integrity (SI) performance is evaluated by analyzing its frequency response up to 100 GHz and its eye diagram. Using this TSV-CAP, the power distribution network (PDN) impedance is kept below 50 mΩ up to 5 GHz while achieving data rate of 5 Gbps.

3 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed.
Abstract: In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed. The study to compare the performance of PCB with ECM versus conventional dielectric FR4 material was conducted with post-layout power integrity simulation using Keysight ADS on the power net of interest, followed by measurement of PDN impedance and simultaneous switching noise (SSN) using network analyzer (VNA) and oscilloscope respectively on prototype PCB. Lastly, eye diagram and jitter of the high frequency clock signal on the PCB are observed. The correlated simulation and measurement results are presented and discussed in the later section of this paper.

3 citations

Proceedings ArticleDOI
01 Jun 2021
TL;DR: In this paper, a 21mm × 14mm interposer is embedded into an electric package, allowing the interposers to work as a bridge between the two chips, and to provide high-density and high-pin-count interconnects.
Abstract: Traditional heterogeneous integrated package structure actually uses several complete IC packages, while the final heterogeneous integrated package structure is completed by restacking and packaging of various IC packages. However, the relatively large package volume, low-density interconnections and low circuit density cannot meet the demand for lighter products. There are still many issues remained in the heterogeneous integration process due to the fact that each chip has its own chip size, material properties, and device type. In order to integrate various heterogeneous chips, a new chip stacking technology is necessary to simplify and reduce the packaging structure, which is used for multi-chip and multi-layer heterogeneous integrated packaging structures as well as obtaining high performance and high bandwidth density. A novel EIC (Embedded interposer carrier) heterogeneous integrated packaging technology is developed to provide SOC-like multi-layer and multi-chip stacking capabilities, which is similar to chiplet concept. In this work, a 21-mm × 14-mm interposer is embedded into an electric package, allowing the interposer to work as a bridge between the two chips, and to provide high-density and high-pin-count interconnects. The external dimension of these two chips is 9 mm × 9 mm and the chip thickness is 100µm. The electrical performance including the power integrity/signal integrity analysis was evaluated by designed test patterns. Daisy chain and Kelvin structure were also included in the testing structure. This new packaging structure is compatible with fan-out packaging technology and enables integration for different chips in order to achieve performance related to 3D IC with a low cost.

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852