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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


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Proceedings ArticleDOI
01 Aug 2017
TL;DR: A simulation methodology that incorporates derating models of decoupling capacitors for power integrity analysis that achieves high accuracy, which is demonstrated through correlations with measurements.
Abstract: In this work, we propose a simulation methodology that incorporates derating models of decoupling capacitors for power integrity analysis. The construction of the derating models of decoupling capacitors is based on the impedance measurement and curve fitting method. Three approaches of impedance measurement are compared and the most accurate one is selected to build the derating models. The curve fitting method converts the measured impedance into circuit models. A library file containing the derating models is generated such that it can be repeatedly used for different products at various design cycles. The derating library takes into account the operation conditions such as temperature and DC bias as well as the vendor information. The proposed simulation methodology with the derating library achieves high accuracy, which is demonstrated through correlations with measurements.

3 citations

Proceedings ArticleDOI
01 Oct 2017
TL;DR: A specific three layer structure is used to study the coupling among closely located ports which connect the two layers of port connected models for PDN applictions.
Abstract: Port-connected models are widely used in many applications such as printed circuit board models. Much compute time can be saved by using only ports to connect the printed circuit board layers. The accuracy of port connected models is investigated in this paper for the relevant frequency range for PDN applictions. In this short paper, we use a specific three layer structure to study the coupling among closely located ports which connect the two layers.

3 citations

Proceedings ArticleDOI
01 Jul 2018
TL;DR: A novel type of EBG structures is proposed to suppress the noise on the printed circuit board (PCB) and achieves the effect of ultra-wideband high isolation and meets the power and signal integrity requirements of high-speed mixed-signal backplane based on VPX(VITA 46).
Abstract: In this paper, the problem of simultaneous switching noise (SSN) in the design of high-speed mixed-signal backplane is analyzed from the aspect of power integrity. How to suppress SSN of high-speed mixed-signal backplane becomes an important research direction at present. Based on the analysis of the traditional decoupling capacitor noise reduction method and the latest noise reduction principle of the electromagnetic band gap (EBG) structures, a novel type of EBG structures is proposed to suppress the noise on the printed circuit board (PCB). The simulation and measurement results show that the noise isolation depth reaches −40dB in the frequency band from 0.4 to 20GHz, which achieves the effect of ultra-wideband high isolation and meets the power and signal integrity requirements of high-speed mixed-signal backplane based on VPX(VITA 46). It provides an experimental reference for the application of the EBG structure on other high-speed mixed-signal backplane and other projects.

3 citations

Journal ArticleDOI
TL;DR: Systemic decoupling capacitors (decaps) optimization strategies that optimally trade-off between power integrity and leakage saving are proposed that can be increased significantly compared with the conventional PDN design approach with a single supply voltage level without jeopardizing power integrity.
Abstract: Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount of power saving intrinsically trades off with power integrity. In addition, these trade-offs significantly vary with supply voltage. In this article, we propose systemic decoupling capacitors (decaps) optimization strategies that optimally trade-off between power integrity and leakage saving. Specially, new global decap and reroutable decap design concepts are proposed to relax the tight interaction between power integrity and leakage saving of power gated PDNs with a single supply voltage level. Furthermore, we propose a flexible decap allocation technique to deal with the design trade-offs under multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing the optimal amount of local decaps, global decaps and reroutable decaps. The conducted experiments demonstrate that leakage saving can be increased significantly compared with the conventional PDN design approach with a single supply voltage level using the proposed techniques without jeopardizing power integrity. For PDN designs operating at two supply voltage levels, the optimal performance is achieved at each voltage level.

3 citations

01 Jan 2009
TL;DR: The impact of split and slotted planes is examined using both measured and simulated data to examine the impact of signal traces on power integrity and signal integrity.
Abstract: Power and/or ground splits and slots frequently arise in real-world boards to manage the various constraints placed on the board designer. As a consequence, signal traces can often be forced to cross these plane split and slot boundaries or routed in close proximity to them. These trace routes may have a number of undesirable consequences on both signal integrity and power integrity. In this paper, we will examine the impact of split and slotted planes using both measured and simulated data.

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852