Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator

Abstract: Power delivery network (PDN) is a distributed resistance-inductance-capacitance (RLC) network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on the high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing instruction loop induced PDN resonance noise at the runtime.

Optimal Power Distribution Network Design for High-Performance Solid-State-Drive Based on Novel Target-Impedance Extraction Method

Abstract: In this paper, we proposed a novel methodology to offer power distribution network (PDN) design guide for PCB power integrity (PI) design for high performance solid-state-drive (SSD). Compared with conventional target-impedance (Z) formulated by current profile of a chip power model (CPM), the proposed methodology utilizes a measurement based current spectrum and a hierarchical PDN-Z model. In order to solve the fundamental limitations of the narrow-banded CPM current model, we successfully measured the PCB-level current of memory packages consisting of the SSD device and converted the measured current values to the chip-level current values using Y-matrix of the hierarchical PDN-Z model consisting of a PCB, a test interposer, a package, and a chip. High-capacity SSD devices are too expensive to make PCBs for design of experiments to test device performance with current measurement. Therefore, we made a test interposer to measure cost-efficiently a current spectrum for each specific power-domain of a unit package such as a DRAM, a NAND, and a SSD controller that all consisting of a SSD device without disturbing SSD’s normal operations.

PI/SI consideration for enabling 3D IC design

Abstract: In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.

On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips

Abstract: An on-chip monitoring technique has realized in place diagnosis of power noise problems. On-chip voltage noise monitor (OCM) circuits are overviewed with some examples of integration in silicon chips. The OCM captures power noise waveforms in a silicon chip and provides the opportunities of diagnosis on unfavorable invisible events within a die. In-band interference of radio-frequency (RF) communication channels by power noise coupling in RF systems-on-chip (SoC) integration, and information leakage through power noise side channels from a cryptographic core are demonstrated.

Some aspects on modeling of the signal and power integrity in a PCB based on waveform analysis

Abstract: This paper presents some of the issues of signal and power integrity in relation with appropriate modeling and simulation methods that are available. The clock signal of a communication protocol is experimentally tested in order to find the rules to improve its signal integrity (SI) along the paths on the printed circuit board (PCB). The signal and power integrity of this PCB are improved using a set of experimental rules based on results of an experimental case study over signal routes. The experimental results obtained are compared with those given by the auto routing function of the design environment. Thus, some improvements of signal integrity along the route clock are highlighted. This set of rules applied to PCB design is validated by the experiment and simulation results.