Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Signal and power integrity analysis for the novel power plane of EBG structure in high-speed mixed signal systems

Abstract: In this paper, a novel power plane of electromagnetic bandgap (EBG) structure for wideband mitigation of simultaneous switching noise (SSN) in mixed signal systems is proposed. Complementary split ring resonator (CSRR) with inherent filtering characteristic is utilized for constituting EBG unit cells. From the simulated and measured results of the proposed EBG structure, a wideband suppression of SSN ranges from 0.56 GHz to 5.88 GHz is achieved with a high mitigation level of -40 dB. Furthermore, the influence of the proposed power plane of EBG structure on the signal integrity (SI) is investigated in the time and frequency domains, respectively. The results show that the SI performance can be improved significantly by using differential pairs for the signals.

Ultra-low ESL capacitor based on Silicon technology with substrate embedded platform

Abstract: As system on chip (SOC) has evolved to integrate more functions in semiconductor integrated circuit (IC), the market needs more advanced wafer fabrication technology which can implement low power system. With this change, the voltage fluctuation problem of low power has been more and more critical so, the engineers had tried to find effective solution to resolve the power delivery issue. Chip capacitors had been placed onto surface of substrate firstly, and capacitors had been moved into substrate for embedding with some applications to reduce the distance between SOC die and capacitor, resulted in performance improvement of power. But, impedance reducing of voltage has been remaining issue as the operating frequency of IC has been increased dramatically. Several ceramic capacitors for reducing equivalent series inductance (ESL) have been developed to overcome such kinds of issue and also, thin film capacitor has been suggested as another novel approach. Deep trench silicon capacitor based on silicon wafer fabrication processing technology has been utilized as one of effective way for device performance improvement. The authors present power integrity (PI) and thermally enhanced a new Si-based capacitor promising low ESL, high density capacitance and low z-profile form-factor, which is implemented by employing the legacy fabrication process which had been used for high density capacitor cell in DRAM (dynamic random access memory). We had noticed that the proven technology in DRAM products could be one of the best solution to make extremely low ESL capacitor. One of the most critical factors to determine the product success of mobile device is to achieve the competitive form factor including package height. This ultra low ESL capacitor is also very effective solution to make ultra thin profile capacitor and competitive package height eventually without sacrificial of capacitance at all. Here, we provide the comparative study of ultra low ESL silicon capacitor and conventional ceramic capacitor with substrate embedded platform for mobile SOC products. Power Delivery Network analysis based on the various structure and design options will be provided. In terms of ESL of capacitor and Z of PDN, while the low ESL ceramic capacitor called by LICC has ESL larger than 60 pH, the presented Si-based capacitor has ESL smaller than 3pH, which eventually reduces the peak value in self-impedance of PDN by 50%. Thermal performance analysis is performed also with various scenarios of mobile applications. With the electrical and thermal performance simulation analysis, the impact of new technology presented in this work on voltage drop of SOC package will be demonstrated through performance measurement evaluation finally. Actual SOC product for premium smartphone with package on package (POP) format will be used for the evaluation.

Power distribution network design from charge delivery perspective

Abstract: In high-speed electrical system design, power integrity (PI) has become critical in designing a power distribution network (PDN). In this paper, a time-domain PDN design method is proposed from a charge delivery perspective. Firstly, the integrated circuit (IC) switching current, drawn from the PDN, is expanded into a series of triangular currents. Next, charge delivery models are presented for ideal passive components and a PDN consisting of these components. Finally, the PDN charge delivery model is combined with the IC switching current (expressed as a summation of triangular currents) to develop the time-domain PDN design method. A practical case study is demonstrated at the end of the paper to validate the proposed PDN design method.

Physical design method of MPSoC

Abstract: Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.

Dynamic Supply Current Waveform Estimation with Standard Library Information

Abstract: In the nanometer era, the power integrity problem has become one of the critical issues. Although checking this problem earlier can speed up the analysis, not so many tools are available now due to the limited design information at high levels. Most existing approaches at gate level require extra information of the cell library, which may require extra characterization efforts while migrating to new cell libraries. Therefore, an analytical approach is proposed in this paper to dynamically estimate the supply current waveforms at gate level using existing library information only, even for sequential circuits. The experimental results have shown that the estimation errors of such a quick approach are only 10% compared to HSPICE results.