Power supply rejection ratio

Abstract: Efficiency and linearity of the microwave power amplifier are critical elements for mobile communication systems. This paper discusses improvements in system efficiency that are obtainable when a DC-DC converter is used to convert available battery voltage to an optimal supply voltage for the output RF amplifier. A boost DC-DC converter with an operating frequency of 10 MHz is demonstrated using GaAs heterojunction bipolar transistors. Advantages of 10 MHz switching frequency and associated loss mechanisms are described. For modulation formats with a time-varying envelope, such as CDMA, the probability of power usage is described. Gains in power efficiency and battery lifetime are calculated. An envelope detector circuit with a fast feedback loop regulator is discussed. Effects of varying supply voltage with respect to distortion are examined along with methods to increase system linearity.

Abstract: A contactless power supply has a dynamically configurable tank circuit powered by an inverter. The contactless power supply is inductively coupled to one or more loads. The inverter is connected to a DC power source. When loads are added or removed from the system, the contactless power supply is capable of modifying the resonant frequency of the tank circuit, the inverter frequency, the inverter duty cycle or the rail voltage of the DC power source.

Abstract: the output amplifiers requiring a bias voltage can be activated or deactivated individually, and a bias acceleration circuit for rapidly increasing the magnitude of a bias voltage in time can be provided in or with the bias circuit, whereby even in case of the capacitance of the capacitor included in the bias circuit being increased for improving the power supply rejection ratio (PSRR), the rise in the bias voltage can be increased so that the pop sound which arises when the bias circuit is activated can be still diminished.

Abstract: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

Abstract: Rotary traveling-wave oscillators (RTWOs) represent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network becomes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differential transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360/spl deg/) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25-/spl mu/m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5,5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements.