Showing papers on "PowerPC published in 2016"
TL;DR: The MPSoCBench is presented, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with up to 64 cores, cross-compilers, IPs, interconnections, 17 parallel versions of software from well-known benchmarks, and power consumption estimation for main components.
5 citations
Patent•
03 Feb 2016
TL;DR: In this article, a bootstrap program, an operation system, an application program and an FPGA loading program are stored in a Flash chip of the PowerPC motherboard. And each program comprises a main program document and a corresponding backup program document respectively correspond to independent check documents.
Abstract: Provided is a remote upgrade system and method of a PowerPC motherboard. A bootstrap program, an operation system, an application program and an FPGA loading program are stored in a Flash chip of the PowerPC motherboard. Each program comprises a main program document and a corresponding backup program document. Each main program document and each backup program document respectively correspond to independent check documents. After program documents are finished backing-up and transmitting, the local PowerPC motherboard is used for computing the check documents again and making comparisons between new check documents and old check documents prior to backup and transmission. If results agree, backup or transmission is finished; but if does not, old versions are reverted. The remote upgrade system and the method of the PowerPC motherboard have following beneficial effects: when the invention is utilized for update, no device cannot be started despite of document transmission and copy errors and damaged documents in a main program area caused by power failure and other accidents during an update process; and therefore remote reliable update is ultimately achieved.
5 citations
12 Dec 2016
TL;DR: In this article, an optimal control framework that takes advantage of feeding back information of finished tasks is proposed to solve a real-time multiprocessor scheduling problem with uncertainty in task execution times, with the objective of minimizing the total energy consumption.
Abstract: Real-time scheduling algorithms proposed in the literature are often based on worst-case estimates of task parameters and the performance of an open-loop scheme can therefore be poor. To improve on such a situation, one can instead apply a closed-loop scheme, where feedback is exploited to dynamically adjust the system parameters at run-time. We propose an optimal control framework that takes advantage of feeding back information of finished tasks to solve a real-time multiprocessor scheduling problem with uncertainty in task execution times, with the objective of minimizing the total energy consumption. Specifically, we propose a linear programming-based algorithm to solve a workload partitioning problem and adopt McNaughton's wrap around algorithm to find the task execution order. Simulation results for a PowerPC 405LP and an XScale processor illustrate that our feedback scheduling algorithm can result in an energy saving of approximately 40% compared to an open-loop method.
4 citations
Patent•
11 May 2016
TL;DR: In this paper, a low-power consumption and high-performance processing module and a construction method of the module is proposed, which is based on a PowerPC P series or T series dual-core or four-core processor.
Abstract: The invention proposes a low-power consumption and high-performance processing module and a construction method thereof. The processing module is a POWERPC low-power consumption P series or T series dual-core or four-core processor, two processors are arranged, the processing performance of the processor is larger or equal to 9.2GIPS, a dynamic random-access memory (RAM) storage, a FLASH storage and an nvRAM storage are configured in each processor, a network communication interface is arranged in the processing module and is implemented by adopting a system on chip (SOC), the network data is exchanged with the dynamic RAM storage through a direct memory access (DMA) mode, a programmable control logic unit is arranged in the processing module and adopts a complex programmable logic device (CPLD) chip, a processor working frequency register and a FLASH storage enable register are arranged, and processing module working condition monitoring and processing module fault management and control are arranged. The invention provides the low-power consumption and high-performance processing module, the module reliability is improved by substantially reducing the power consumption of the module, meanwhile, the module is more universal, and the application environment and the application field of the module are expanded.
4 citations
01 Jan 2016
TL;DR: This chapter presents a generic DPR manager core that has been optimized to provide high reliability, results are shown in terms of performance, resources utilization and fault tolerance capability, which reinforce its advantages over traditional solutions.
Abstract: Critical applications must rely on fault-tolerant systems in order to guarantee an error-free execution since the cost of a system fault can be paid in terms of millions of dollars or, even worse, in terms of human lives. In this context, Dynamic Partial Reconfiguration (DPR) enables a more optimized and reliable usage of state-of-the-art Xilinx SRAM-based Field Programmable Gate Arrays (FPGA) resources over space and time. DPR techniques make use of the Internal Configuration Access Port (ICAP), an internal FPGA interface that allows changing on the fly the functionality of a portion of its logic. Unfortunately, a standard DPR flow requires the use of at least a microprocessor (MicroBlaze, PowerPC or ARM), extra memories due to the microprocessor and several peripherals, which results in dense and complex designs that may be easily corrupted by radiation incidence. This chapter presents a generic DPR manager core that has been optimized to provide high reliability. Results are shown in terms of performance, resources utilization and fault tolerance capability, which reinforce its advantages over traditional solutions.
3 citations
Patent•
21 Sep 2016
TL;DR: In this paper, a high-power wind-power conversion system based on the EtherCAT communication has been presented, where the power units and control cores are modularized, and an Ether-CAT internal bus is adopted, so that the probability in implementation of wind power converters of different capacities is increased greatly.
Abstract: The invention provides a high-power wind-power conversion system based on EtherCAT communication. The high-power wind-power conversion system comprises a core control CPU (Central Processing Unit) and at least one power unit, wherein the core control CPU is a powerPC processor; and each power unit comprises a signal acquisition unit, a core computing unit, a PWM (Pulse-Width Modulation) unit, a driving unit and an output unit which are in a signal connection in sequence. The high-power wind-power conversion system based on the EtherCAT communication has the beneficial effects that the power units and control cores are modularized, and an EtherCAT internal bus is adopted, so that the probability in implementation of wind-power converters of different capacities is increased greatly; different application demands in the industry can be met truly through one-time development; a good development platform is provided for secondary development of other systems; the development periods of new products are greatly shortened; and the manpower and material resource cost is reduced at the same time.
3 citations
TL;DR: In this article, the preliminary architecture of instrument control unit (ICU) is described, which is aimed at operating all X-ray Integral Field Unit (X-IFU) subsystems, as well as at implementing the main functional interfaces of the instrument with the S/C control unit.
Abstract: Athena is one of L-class missions selected in the ESA Cosmic Vision 2015-2025 program for the science theme of the Hot and Energetic Universe. The Athena model payload includes the X-ray Integral Field Unit (X-IFU), an advanced actively shielded X-ray microcalorimeter spectrometer for high spectral resolution imaging, utilizing cooled Transition Edge Sensors. This paper describes the preliminary architecture of Instrument Control Unit (ICU), which is aimed at operating all XIFU’s subsystems, as well as at implementing the main functional interfaces of the instrument with the S/C control unit. The ICU functions include the TC/TM management with S/C, science data formatting and transmission to S/C Mass Memory, housekeeping data handling, time distribution for synchronous operations and the management of the X-IFU components (i.e. CryoCoolers, Filter Wheel, Detector Readout Electronics Event Processor, Power Distribution Unit). ICU functions baseline implementation for the phase-A study foresees the usage of standard and Space-qualified components from the heritage of past and current space missions (e.g. Gaia, Euclid), which currently encompasses Leon2/Leon3 based CPU board and standard Space-qualified interfaces for the exchange commands and data between ICU and X-IFU subsystems. Alternative architecture, arranged around a powerful PowerPC-based CPU, is also briefly presented, with the aim of endowing the system with enhanced hardware resources and processing power capability, for the handling of control and science data processing tasks not defined yet at this stage of the mission study.
2 citations
Patent•
17 Feb 2016
TL;DR: In this paper, a universal single-board computer module consisting of a POWERPC processor, a programmable logic device, a temperature sensor, an LED (light-emitting diode), an FPGA(Field Programmable Gate Array), an Ethernet port, VPEX, an Ethernet transceiver, a VPX connector P0, an SRIO switch and a nonvolatile flash memory is presented.
Abstract: The invention discloses a universal single-board computer module. The universal single-board computer module comprises a POWERPC processor, a programmable logic device, a temperature sensor, an LED (light-emitting diode), an FPGA(Field Programmable Gate Array), an Ethernet port, an Ethernet port VPEX, an Ethernet transceiver, a VPX connector P0, an SRIO switch and a nonvolatile flash memory, wherein the POWERPC processor is respectively connected with an internal memory, the temperature sensor, the VPX connector P0, the Ethernet transceiver, a serial port, the SRIO switch, a PCLe-USB convertor and the programmable logic device. The universal single-board computer module has the advantages of high processing speed, high memory capacity, high control accuracy, temperature monitoring function, power supply managing function and multi-software support.
2 citations
Patent•
14 Dec 2016
TL;DR: In this article, a monitoring method for hardware performance and a system is presented, which is applied to a host processor in which a VxWorks operation system runs and a PowerPC framework is adopted.
Abstract: The invention discloses a monitoring method for hardware performance and a system. The monitoring method is applied to a host processor in which a VxWorks operation system runs and a PowerPC framework is adopted. The method comprises the following steps: utilizing the host processor to analyze a configuration message sent by a client, thereby acquiring a monitoring period and all the monitored events; applying a time division multiplex access algorithm to the fluctuation weighted values corresponding to the monitoring period, all the monitored events and the pre-stored monitored events, thereby generating a monitoring configuration document; acquiring the practical happening times of the monitored events according to the monitoring configuration document; calculating and acquiring the forecast happening times of the monitored events; packing the monitored events and the forecast happening times of the monitored events into a result message and sending to the client, thereby realizing the monitoring for the hardware performance.
2 citations
Patent•
16 Nov 2016
TL;DR: In this paper, a nuclear core plate based on powerPC configures central processing unit, including central processing units, field programmable gate array, complex programmable logic device, power module, the module that resets, clock module, communication unit and memory cell.
Abstract: The utility model discloses a nuclear core plate based on powerPC configures central processing unit, including central processing unit, field programmable gate array, complex programmable logic device, power module, the module that resets, clock module, communication unit and memory cell, field programmable gate array and central processing unit are connected, and complex programmable logic device is connected with central processing unit, field programmable gate array, power module, the module that resets and clock module, communication unit includes gigabit ethernet module, gigabit ethernet switch and the RS232 transceiver of being connected with field programmable gate array, RS422 transceiver, the LVTTL buffer of being connected with central processing unit, memory cell includes DRAM, eMMC and the SSD who is connected with central processing unit. The utility model provides a nuclear core plate, the integrated level is high, small, the peripheral hardware interface is abundant, being suitable for integratedly to user's target integrated circuit board in, shortens product development time of designer.
2 citations
Patent•
23 Mar 2016
TL;DR: In this paper, a PowerPC processor-based performance monitoring method is presented, which consists of the following steps: 1) constructing a graphic configuration tool and a performance monitoring module; 2) making a performance measurement scheme, wherein the performance monitoring scheme comprises a software object required to be monitored, an event required to monitor, and a monitoring triggering mode; 3) generating a configuration data file by utilizing the graphic configuration tools through the made performance monitoring schemes; 4) loading the configuration data files to a target machine; and 5) running the target machine to obtain performance monitoring data.
Abstract: The invention belongs to the field of computer software and relates to the field of performance evaluation, in particular to a PowerPC processor based performance monitoring method. The method comprises the following steps: 1) constructing a graphic configuration tool and a performance monitoring module; 2) making a performance monitoring scheme, wherein the performance monitoring scheme comprises a software object required to be monitored, an event required to be monitored, and a monitoring triggering mode; 3) generating a configuration data file by utilizing the graphic configuration tool through the made performance monitoring scheme; 4) loading the configuration data file to a target machine; and 5) running the target machine to obtain performance monitoring data. With the method, few system resources are consumed and processor-level performance data unavailable for conventional testing and evaluation can be obtained.
TL;DR: The simulated results using finer technologies with Synopsys HSPICE prove that PowerPC 603 is a resilient flip-flop for all corners.
Abstract: Flip-flops are the basic building blocks of any sequential circuits which occupy the maximum area in a circuit. So the robustness of the system greatly depends on the reliable operation of the flip-flop. In this work the PowerPC 603 flip-flop is simulated and analyzed to measure its reliability against variations in supply voltage and temperature. Performance analysis has been made by having Power, Delay and PDP as Figures of Merit. The acquired simulation results revealed the different sources of power consumption in different scenarios. The simulated results using finer technologies with Synopsys HSPICE prove that PowerPC 603 is a resilient flip-flop for all corners.
Patent•
04 May 2016
TL;DR: In this article, the utility model discloses a computer processing integrated circuit board, including POWERPC treater, programmable logic device, temperature sensor, real-time clock, LED module, ether net gape, guang kou, ethernet transceiver, SRIO interface and nonvolatile flash memory.
Abstract: The utility model discloses a computer processing integrated circuit board, including POWERPC treater, programmable logic device, temperature sensor, real -time clock, LED module, ether net gape, guang kou, ethernet transceiver, SRIO interface and non -volatile flash memory, memory, temperature sensor, real -time clock, electricity are connected respectively to the POWERPC treater can wipe programmable ROM, ethernet transceiver, serial ports, SRIO interface, PCLe converter and programmable logic device The utility model discloses computer processing integrated circuit board has following advantage: 1, use 1 48 way PCIE 20 switch chip 2, support vxWorks 68 more than or, fully provided radar, video image handle, crucial real -time among the intelligent signal processing 3, superstrong environmental suitability, operating temperature: - 40 DEG C ~+ 85 DEG C Adapt to the application under national defence military project and the aviation field adverse circumstances
Patent•
06 Jan 2016
TL;DR: In this article, a method for a POWERPC cloud storage platform to realize SAN (Storage Area Networking) by using LIO (Linux-IO), which belongs to the field of cloud storage platforms, is presented.
Abstract: The present invention discloses a method for a POWERPC cloud storage platform to realize SAN (Storage Area Networking) by using LIO (Linux-IO), and belongs to the field of cloud storage platforms The method comprises: in a Yocto system constructed by a Power PC, configuring and compiling modules related to LIO into a kernel by using a bitbake tool; writing an LIO management tool targetcli and a Qlogic FC card drive, and formulation files of qla2 x x x, and compiling the LIO management tool targetcli, the Qlogic FC card drive and the formulation files of qla2 x x x into a file system; downloading the kernel and the file system to a PowerPC controller; and realizing application of IP-SAN and FC-SAN by using targetcli configuration The implementation method provided by the present invention is simple, reliable, low in cost, excellent in performance, can realize wide application of LIO in an SAN aspect of the PowerPC cloud storage platform, and is economically good
03 Mar 2016
TL;DR: This paper has simulated the performance of PowerPC603 flip-flop in subthreshold region using Nano scale CMOS devices below 16nm till 7nm using BSIM-CMG (a compact model for the class of common multi-gate FETs) and EKV model extracted from BSIM.
Abstract: The pertinent choice of D flip-flop is an indispensible cell in any logic cell library. The transitions in flip-flop dictates power consumption in sensor nodes. Power-Delay-Area are the Figures of Metric (FoM) which decides the choice of flip-flop used in wireless sensor nodes (WSN). In this paper, we identified PowerPC 603 flip-flop as the candidate suitable for WSN after conducting robust analysis of several flip-flop circuits proposed in literature. Subthreshold design is an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. To set the tone in current context, we have simulated the performance of PowerPC603 flip-flop in subthreshold region using Nano scale CMOS devices below 16nm till 7nm using BSIM-CMG (a compact model for the class of common multi-gate FETs) and EKV model extracted from BSIM-CMG models. Simulations are carried out with HSPICE (Level=55) and the performance of PowerPC 603 flip-flop are analyzed for the two models. The minimum Power Delay Product (PDP) is 510 aJ and 18.35 aJ for 14nm technology in BSIM-CMG and EKV models respectively at 0.3V.
Patent•
13 Jul 2016
TL;DR: In this article, a display card accelerator based on vxworks, including powerPC module, FPGA module, display card processing module and a connector of outer connector with higher speed, is presented.
Abstract: The utility model discloses a display card accelerator based on vxworks, including powerPC module, FPGA module, display card processing module and be used for the connector of outer connector with higher speed, interconnect's powerPC module, FPGA module are connected with the connector through display card acceleration processing module respectively, display card processing module with higher speed includes 1 tunnel VGA interface that adopts the VGA chip of connecting powerPC treater and connector. The utility model discloses a based on vxworks's powerPC and the mode that the VGA chip combined together, realize the demonstration with higher speed of 2D figure, have higher ageingly, can satisfy the application request of industry or space flight.
Patent•
16 Nov 2016
TL;DR: In this paper, a general nuclear core plate based on powerPC configures central processing unit, including central processing units, field programmable gate array, communication unit, memory cell, temperature sensor and real-time clock module, where the integrated level is high, small, the peripheral hardware interface is abundant, being suitable for integratedly to user's target integrated circuit board in, shortens product development time of designer.
Abstract: The utility model discloses a general nuclear core plate based on powerPC configures central processing unit, including central processing unit, field programmable gate array, communication unit, memory cell, temperature sensor and real -time clock module, wherein, does field programmable gate array pass through PCI E interface, SRIO interface, LBC interface, GPIO interface and IRQ interface are connected with central processing unit, communication unit includes general asynchronous receiving and dispatching transmitter and ethernet module, and general asynchronous receiving and dispatching transmitter passes through the RS232 interface and is connected with central processing unit to too the wire mould piece passes through II interfaces of RGM and is connected with central processing unit, memory cell includes SD card, norFlash, nandFlash, USB controller and DDR3, and nandFlash passes through eLBC interface connection central processing unit, and DDR3 passes through the memory controller and connects central processing unit. The utility model provides a general nuclear core plate, the integrated level is high, small, the peripheral hardware interface is abundant, being suitable for integratedly to user's target integrated circuit board in, shortens product development time of designer.
Patent•
09 Nov 2016
TL;DR: In this paper, a control system of a charger consisting of a DSP unit, a PowerPC unit and an upper computer is presented. And the control method and the control system have advantages of remote monitoring, convenient maintenance, and stable operation.
Abstract: The invention discloses a control system of a charger. The control system comprises a DSP unit, a PowerPC unit and an upper computer. The DSP unit and the PowerPC unit carry out mutual communication by a dual-port RAM unit; and the upper computer and the PowerPC unit are in communication connection by an Ethernet network, thereby realizing remote real-time monitoring and maintenance on a charger. In addition, the invention also discloses a control method of a charger. The upper computer sends a command signal to the PowerPC unit by an Ethernet network; the PowerPC unit b receives the command signal from the upper computer and then sends the signal to the DSP unit by the dual-port RAM unit; and the DSP executes a corresponding motion based on the command signal of the upper computer. The control method and the control system have advantages of remote monitoring, convenient maintenance, and stable operation.
Patent•
07 Dec 2016
TL;DR: In this paper, an FPGA boot loading FLASH upgrade system based on a PowerPC processor and a VMs is presented. But the system is not suitable for large-scale applications.
Abstract: The invention provides an FPGA boot loading FLASH upgrade system based on an FPGA and a PowerPC The FPGA boot loading FLASH upgrade system comprises a PowerPC processor, an FPGA chip, an FLASH chip and a data transmission module for implementing data transmission; the PowerPC processor is connected with the FPGA chip by a Local Bus, and the PowerPC processor is connected with an address high 2-bit of the FLASH chip by a GPIO pin of a 2-bit; an FPGA bus conversion module for converting a Local Bus interface into an FLASH interface is arranged in the FPGA chip An FPGA boot loading FLASH upgrade method based on the FPGA and the PowerPC comprises the following steps of: S1, generating binary files corresponding to four FPGA versions which need to be automatically converted in a Vivado; S2, writing one random FPGA version of bit file into the FPGA chip by a JTAG downloader; and S3, by the PowerPC processor, controlling switching of the address high 2-bit of the FLASH chip to form four FLASH storage spaces, and by the PowerPC processor, sequentially programming each FPGA version in the FPGA chip into the corresponding FLASH storage space According to the FPGA boot loading FLASH upgrade system and the FPGA boot loading FLASH upgrade method which are provided by the invention, flexibility and functionality of application are improved