Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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10 Oct 1999
TL;DR: The paper evaluates the area, performance, and yield impact of several different implementations of on-chip cache redundancy in the context of the next member of Motorola's G4 generation of PowerPC/sup TM/ processors.
Abstract: To meet increasing system performance demands, microprocessor designers continue to expand the amount of cache memory integrated on the processor die. The resulting additional silicon area has the undesirable effects of reducing die yield and increasing die cost. Adding redundancy to the on-chip caches can mitigate the reduced yield but introduces additional penalties in die area and performance. The paper evaluates the area, performance, and yield impact of several different implementations of on-chip cache redundancy in the context of the next member of Motorola's G4 generation of PowerPC/sup TM/ processors (N. Iyengar, 1999).
7 citations
28 Mar 1998
TL;DR: This work uses the superscalar PowerPC 604 as an example to show that such processors still benefit from more broadly scoped scheduling at compile time, and reuse an existing retargetable V LIW compiler environment by instantiating it for a VLIW processor whose resources and instructions resemble those of the PowerPC.
Abstract: Efficient use of multiple functional units in superscalar processors requires instruction level parallelism to be detected and exploited. Thus special hardware in the form of dispatch units is used to uncover scheduling opportunities within an instruction window at run-time. Using the superscalar PowerPC 604 as an example we show that such processors still benefit from more broadly scoped scheduling at compile time. In our approach we reuse an existing retargetable VLIW compiler environment by instantiating it for a VLIW processor whose resources and instruction timings resemble those of the PowerPC.
7 citations
IBM1
TL;DR: Several aspects of the &i1 design are described and some of the design trade-offs considered in those areas are discussed, including competitive performance and cost, compatibility with existing POWER applications, and support for multiprocessing.
Abstract: The PowtrPC 601TM microprocessor (601) is the first memlier of a tamily of processors that support IBM's PowerPC Architecture\"\". The 601 Is a general-purpose processor based on a superscalar design point. As with any development effort, the 601 development program had several different, often conflicting, design goals. The most important requirements were support for the PowerPC Architecture, a short development cycle, competitive performance and cost, compatibility with existing POWER applications, and support for multiprocessing. This paper describes several aspects of the &i1 design and discusses some of the design trade-offs considered in those areas.
7 citations
TL;DR: From the 1956 IBM 7030 (Stretch) to today's PowerPC, this work presents queue configurations and prefetch strategies along with the design decisions that led to their final architectures.
Abstract: For several decades, designers have used queues to resolve two processor-memory interface problems - long latency and low bandwidth. Here, we discuss the evolution of instruction and branch target queues. We also explore their use to support variable-length instructions and reduce misalignment problems. From the 1956 IBM 7030 (Stretch) to today's PowerPC, we present queue configurations and prefetch strategies along with the design decisions that led to their final architectures. >
7 citations
TL;DR: The whole system has been finally commissioned in RFX in only two weeks, with the usage of MARTe allowing a rapid development of the control system and, in particular, its intrinsic simulation ability gave the possibility of carrying out most debugging in simulation, without affecting machine operation.
7 citations