Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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TL;DR: This paper reports work on using the GPU as a parallel processing unit to accelerate the decoding of H.264/AVC high-definition (1920x1080) video.
Abstract: The Xbox 360 is powered by three dual pipeline 32 GHz IBM PowerPC processors and a 500 MHz ATI graphics processing unit The Graphics Processing Unit (GPU) is a special-purpose device, intended to create advanced visual effects and to render realistic scenes for the latest Xbox 360 games In this paper, we report work on using the GPU as a parallel processing unit to accelerate the decoding of H264/AVC high-definition (1920x1080) video We report our experiences in developing a real-time, software-only high-definition video decoder for the Xbox 360
6 citations
15 Mar 2012
TL;DR: Xilinx Platform Studio (XPS) provides an integrated environment for creating software and hardware specification flows for embedded processor systems based on MicroBlaze and PowerPC processors and allows the user to incorporate soft-core processors (MicroBlaze or PicoBlaze) to interface the built-in PowerPC computers with the reconfigurable FPGA resources.
Abstract: The microprocessors available for use in Xilinx Field Programmable Gate Arrays (FPGAs) with Xilinx EDK (Embedded Development Kit) software tools can be divided into two broad categories There are soft-core microprocessors (MicroBlaze) and the hard-core embedded microprocessor (PowerPC) Xilinx Platform Studio (XPS) provides an integrated environment for creating software and hardware specification flows for embedded processor systems based on MicroBlaze and PowerPC processors MicroBlaze is a 32-bit RISC soft-core (synthesizable) processor core that enables embedded developers to tune performance to match the requirements of target applications XPS offers customization of tool flow configuration options and provides a graphical system editor for connection of processors, peripherals, and buses XPS tool can create a simple processor system and the process of adding a custom OPB peripheral to that processor system by using the Import Peripheral Wizard The EDK allows the user to incorporate soft-core processors (MicroBlaze or PicoBlaze) to interface the built-in PowerPC processors with the reconfigurable FPGA resources Such processors can also be used to interface the hardware system to a variety of input/output peripheral devices needed to supply input data to the hardware system through serial communication and/or to display the results of processing
6 citations
Patent•
06 Aug 2014
TL;DR: In this article, a transient characteristic test system of a mutual inductor based on digital simulation of a Rogowski coil is presented, which consists of a signal conditioning module, an optical fiber sending module, optical fiber Ethernet module, a digital analog converter, an FPGA (Field Programmable Gate Array), a POWERPC, a crystal oscillator, a human-computer interface and a storage module.
Abstract: The invention discloses a transient characteristic test system of a mutual inductor based on digital simulation of a Rogowski coil. The system comprises a signal conditioning module, an optical fiber sending module, an optical fiber Ethernet module, a digital analog converter, an FPGA (Field Programmable Gate Array), a POWERPC, a crystal oscillator, a human-computer interface and a storage module, wherein the crystal oscillator is connected with the FPGA and the POWERPC, the FPGA is connected with the digital analog converter, the optical fiber sending module, the optical fiber Ethernet module and the POWERPC, the POWERPC is connected with the storage module and the human-computer interface, and the digital analog converter is connected with the signal conditioning module. The FPGA comprises a synchronization module, a data receiving module and a DAC (Digital-to-Analog Converter) control module. The POWERPC comprises a digital simulation model module of the Rogowski coil, a parameter configuration module, a test data processing module and a transient characteristic analyzing module. Based on an ideal Rogowski coil model, a differential signal output is established for all-digital simulation test to be not limited in individual professional laboratories. Advantages of hardware integration and software integration can be compared, and all-around simulation test of transient characteristics of the electronic mutual inductor can be realized.
6 citations
Patent•
26 Feb 2014
TL;DR: In this article, a multifunctional communication interface machine device based on the PowerPC embedded system is described, which consists of a CPU core board, a mother board, interface boards and a power module.
Abstract: The invention relates to a multifunctional communication interface machine device, in particular to a multifunctional communication interface machine device based on a PowerPC embedded system. The multifunctional communication interface machine device based on the PowerPC embedded system comprises a CPU core board, a mother board, interface boards and a power module. A processor of the PowerPC embedded system is carried by the CPU core board. The mother board serves as a main board of the multifunctional communication interface machine device, and mainly comprises a CPLD circuit, an extension serial port circuit, a bus level conversion circuit, an RTC clock circuit, a CAN interface circuit and a 422/485 interface circuit. The interface boards comprise CAN interface boards and 422/485 interface boards. The CPU core board is connected with the bus level conversion circuit on the mother board, and is connected with the CPLD circuit, the extension serial port circuit and the RTC clock circuit after level conversion. The CPLD circuit is connected with the CAN interface circuit through a bus of the address and data time division multiplexing mode. Four paths of 232 serial interfaces are extended by the extension serial port circuit through a four-channel asynchronous transceiver STC16C554 chip to be connected with the 422/485 interface circuit. The CAN interface boards and the 422/485 interface boards are connected with the CAN interface circuit and the 422/485 interface circuit on the mother board respectively.
6 citations
TL;DR: A two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core so that the Javacore can be encapsulated as a reusable IP.
Abstract: In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.
6 citations