PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Load miss performance analysis methodology using the PowerPC 604 performance monitor for OLTP workloads

Abstract: This paper describes a methodology via which the PowerPC 604 Micro Processor (abbreviated 604 in the remainder of this paper) performance monitor can be used to examine and contrast the effects of hardware variations on system performance. We present performance measurement data and analysis of an On-Line Transaction Processing (OLTP) workload, which are derived via repeated runs using a database software engine with several different memory and processor speeds. We show for our workload that variations in the easily measured load miss sojourn can be used to approximate the valuable but difficult to measure composite cache miss penalty. We also show interesting variations in bus utilization versus bus to processor clock ratios.

IBM Blue Gene Supercomputer

Abstract: Introduction TheIBMBlueGene Supercomputer is amassively parallel system based on the PowerPC processor. It derives its computing power from scalability and energy efficiency. Each computing node of Blue Gene is optimized to achieve high computational rate per unit of power and to operate with other nodes in parallel. This approach results in a system that can scale to very large sizes and deliver substantial aggregate performance. Most large parallel systems in the – time frame followed a model of using off-the-shelf processors (typically from Intel, AMD, or IBM) and interconnecting them with either an industry standard network (e.g., Ethernet or Infiniband) or a proprietary network (e.g., as used by Cray or IBM). Blue Gene took a different approach by designing a dedicated system-on-achip (SoC) that included not only processors optimized for floating-point computing, but also the networking infrastructure to interconnect these building blocks into a large system. This customized approach led to the scalability and power efficiency characteristics that differentiated Blue Gene from other machines that existed at the time of its commercial introduction in . As of , IBM has produced two commercial versions of BlueGene, BlueGene/L andBlueGene/P, which were first delivered to customers in  and , respectively. A third version, Blue Gene/Q, was under development. Both delivered versions follow the same design principles, the same system architecture and the same software architecture. They differ on the specifics of the basic SoC that serves as the building block for Blue Gene. The November  TOP list includes four Blue Gene/L system and ten Blue Gene/P systems (and one prototype Blue Gene/Q system). In this article we cover mostly the common aspects of both versions of the Blue Gene supercomputing and discuss details specific to each version as appropriate.

Developing Custom Firmware for the Red Storm SeaStar Network Interface.

Abstract: The Red Storm SeaStar network interface contains an embedded PowerPC 440 CPU that, out-of-thebox, is used solely to handle network protocol processing. Since this is a fully programmable general purpose CPU, network researchers may wish to program it to perform additional tasks such as NIC-based collective operations and NIC-level computation. This paper describes our experiences developing custom firmware for the SeaStar. In order to make the SeaStar more accessible to non-experts, we have developed a C version of the assembly-based firmware provided by Cray. This high-level language firmware should be much easier to understand and to quickly extend with new features. A detailed overview of the SeaStar programming environment and our C firmware will be presented along with optimization techniques that we have found beneficial.

DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG

Abstract: The implementation and validation of a common DFT architecture for a new product family of PowerPC based microprocessors for various automotive applications supporting highest quality levels and low-cost test is a big challenge. When this new architecture has to satisfy the requirements of two semiconductor companies using two different CAD flows based on different ATPG tools coming with incompatible on-chip scan compression solutions, the task becomes even more complex. This paper describes the result of this major effort and shows the problems encountered along the way.

XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors

Abstract: High-performance processors give opportunities and challenges for development of real-time and embedded applications. New advances in hardware introduce new questions as alternatives to enable multiple applications to share a single processor and memory, so that the high-performance hardware that contains millions of transistors can be fully utilized, as also the way to keep system dependable and stable by making applications stay in spatial and temporal isolation inside same system. It is introduced in this paper XtratuM, a real-time hypervisor designed and implemented based on the concept of a partitioned system, by enabling partitions to execute simultaneously in spatial and temporal isolation without interfering with each other, but sharing the same hardware. Still in this paper, we provide a brief introduction on partitioned systems and its significance, also presenting the prototype implementation of XtratuM on PowerPC architecture including essential parts: hypercalls, timer, interrupt, and memory management implementations. Benchmark applications have been carried out to illustrate that the model implemented by XtratuM is suitable to offer the capability of spatial and temporal isolation under real-time requirements.