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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


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Proceedings ArticleDOI
20 Mar 2018
TL;DR: A testing methodology that automatically infers structural information for an instruction set and uses the inferred structure to efficiently generate structured-random test cases independent of the instruction set being tested is presented.
Abstract: Decoding binary executable files is a critical facility for software analysis, including debugging, performance monitoring, malware detection, cyber forensics, and sandboxing, among other techniques. As a foundational capability, binary decoding must be consistently correct for the techniques that rely on it to be viable. Unfortunately, modern instruction sets are huge and the encodings are complex, so as a result, modern binary decoders are buggy. In this paper, we present a testing methodology that automatically infers structural information for an instruction set and uses the inferred structure to efficiently generate structured-random test cases independent of the instruction set being tested. Our testing methodology includes automatic output verification using differential analysis and reassembly to generate error reports. This testing methodology requires little instruction-set-specific knowledge, allowing rapid testing of decoders for new architectures and extensions to existing ones. We have implemented our testing procedure in a tool name Fleece and used it to test multiple binary decoders (Intel XED, libopcodes, LLVM, Dyninst and Capstone) on multiple architectures (x86, ARM and PowerPC). Our testing efficiently covered thousands of instruction format variations for each instruction set and uncovered decoding bugs in every decoder we tested.

5 citations

Proceedings ArticleDOI
01 Jan 2006

5 citations

Proceedings ArticleDOI
15 Mar 1999
TL;DR: AltiVec obtained significant speedups on autocorrelation computation, linear prediction coefficients computation via Levinson-Durbin method and Schur (1917) recursion and part of the GSM speech compression system.
Abstract: The AltiVec technology is a SIMD (single instruction multiple data) extension to PowerPC architecture. It is intended to provide architectural support for performance improvement of various image and signal processing applications, including speech processing, on a general-purpose processor implementation, such as, the PowerPC line of processors. We have implemented some of the common speech processing algorithms on AltiVec architecture. The algorithms discussed in this paper are autocorrelation computation, linear prediction coefficients computation via Levinson-Durbin method and Schur (1917) recursion and part of the GSM speech compression system. AltiVec obtained significant speedups on all these algorithms, compared to the scalar PowerPC implementation. We also found that additional speedup was achievable by porting to new, more SIMD-friendly algorithm.

5 citations

Proceedings ArticleDOI
06 Nov 1996
TL;DR: This paper discusses the basics of developing "virtual" devices for use with the Windows based development environment provided with Software Development Systems 68 K and PowerPC free sample kits and is in the preliminary development stages of a new HTML Web page approach where it control, rather than just launch, these commercial simulation packages.
Abstract: It is a common problem in industry that the development of software does not go hand-in-hand with the development of the hardware that the software is intended to control. A similar situation can occur in the undergraduate laboratory. Here a student, having designed the software component of a project, can't gain access to the necessary hardware to prepare for or complete a laboratory because of schedule/security difficulties. Over the past year we have overcome this problem by using "virtual" hardware, where device operation is simulated in software. We have generalized the approach so that the virtual devices can be used in conjunction with microprocessor simulator software and with actual evaluation boards for both RISC and CISC systems. We are in the preliminary development stages of a new HTML Web page approach where we control, rather than just launch, these commercial simulation packages. Such an approach would provide a controlled, interactive, tutorial environment for students taking microprocessor courses. There are further industrial and academic advantages of such an approach which can help to overcome the initial learning curve for the tools. We discuss the basics of developing "virtual" devices for use with the Windows based development environment provided with Software Development Systems 68 K and PowerPC free sample kits. These devices can then be ported to the Motorola M68332EVK and Advanced Micro Devices' SA29200 microprocessor evaluation boards to provide actual hardware experience.

5 citations

Journal ArticleDOI
TL;DR: It is observed that 64-bit computing typically results in a significantly larger number of data cache misses at all levels of the memory hierarchy, and that when a sufficiently large heap is available, the IBM JDK 1.4.0 VM is 1.7p slower on average in 64- bit mode than in 32-bit mode.
Abstract: The Java language is popular because of its platform independence, making it useful in a lot of technologies ranging from embedded devices to high-performance systems. The platform-independent property of Java, which is visible at the Java bytecode level, is only made possible thanks to the availability of a Virtual Machine (VM), which needs to be designed specifically for each underlying hardware platform. More specifically, the same Java bytecode should run properly on a 32-bit or a 64-bit VM. In this paper, we compare the behavioral characteristics of 32-bit and 64-bit VMs using a large set of Java benchmarks. This is done using the Jikes Research VM as well as the IBM JDK 1.4.0 production VM on a PowerPC-based IBM machine. By running the PowerPC machine in both 32-bit and 64-bit mode we are able to compare 32-bit and 64-bit VMs. We conclude that the space an object takes in the heap in 64-bit mode is 39.3p larger on average than in 32-bit mode. We identify three reasons for this: (i) the larger pointer size, (ii) the increased header and (iii) the increased alignment. The minimally required heap size is 51.1p larger on average in 64-bit than in 32-bit mode. From our experimental setup using hardware performance monitors, we observe that 64-bit computing typically results in a significantly larger number of data cache misses at all levels of the memory hierarchy. In addition, we observe that when a sufficiently large heap is available, the IBM JDK 1.4.0 VM is 1.7p slower on average in 64-bit mode than in 32-bit mode. Copyright © 2005 John Wiley & Sons, Ltd.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823