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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


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Proceedings ArticleDOI
01 Jun 2000
TL;DR: This semi-custom target platform combines a highly integrated 32-bit embedded Motorola PowerPC processor and two high-density Xilinx FPGAs, allowing plenty of headroom for follow-on student projects and future course expansion.
Abstract: The EECS 373 "Design of Microprocessor-based Systems" course at the University of Michigan ties hardware and software together by providing a modern platform on which students simultaneously develop both hardware and software components of simple systems. Our semi-custom target platform combines a highly integrated 32-bit embedded Motorola PowerPC processor and two high-density Xilinx FPGAs, allowing plenty of headroom for follow-on student projects and future course expansion. Versions of the development tools we employ in the lab are also available, with simulation capabilities, on public workstations and students' personal PCs, enabling students to work outside the lab and maximizing the leverage of finite lab space in the face of growing enrollments.

5 citations

Proceedings ArticleDOI
22 Oct 2004
TL;DR: A low-level compiling technique based on a minimal code generator with parametric embedded sections to generate binary code at run-time for intensively reused functions in graphic applications where the advantages of dynamic compilation have not been fully taken into account yet.
Abstract: Knowledge of data values at run-time allows us to generate better code in terms of efficiency, size and power consumption.This paper introduces a low-level compiling technique based on a minimal code generator with parametric embedded sections to generate binary code at run-time. This generator called a "compilet" creates code and allocates registers using the data input. Then, it generates the needed instructions. Our measurements, performed on Itanium 2 and PowerPC platforms have shown a speed improvement of 43% on the Itanium 2 platform and 41% on the PowerPC one.The proposed technique proves to be particularly useful in the case of intensively reused functions in graphic applications, where the advantages of dynamic compilation have not been fully taken into account yet.

5 citations

Proceedings ArticleDOI
22 Jun 1999
TL;DR: Experiences developing a data acquisition system for the BABAR CP violation experiment located at the Stanford Linear Accelerator Center are presented.
Abstract: Experiences developing a data acquisition system for the BABAR CP violation experiment located at the Stanford Linear Accelerator Center are presented. The BABAR detector consists of multiple independent subdetectors joined with a data acquisition system consisting of a large number of embedded PowerPC single board computers residing in VME crates. The data acquisition software is layered on the VxWorks real-time operating system. It is partitionable to allow subsystems (as well as test stands) to operate independently. Data is assimilated into events through a combination of shared memory and a high performance network. This system presents data to a UNIX farm via a high speed non-blocking ethernet switch at a rate of 2 KHz. Topics such as bootstrapping and loading 200 processors, NFS file access for these processors and software development and deployment are discussed.

5 citations

Proceedings ArticleDOI
Jing Zeng1, M. Abadir1
05 Apr 2004
TL;DR: This paper demonstrates the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.
Abstract: The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to correlate with functional test frequency closely. In this paper, we demonstrate the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.

5 citations

Journal ArticleDOI
TL;DR: The PowerPC AS™ A10 64-bit RISC microprocessor is a 4.7-million-transistor integrated circuit design, using IBM CMOS 5L 0.5-µm, 3-V, four-level-metal ASIC technology, which is robust and implements a wide range of performance configurations at the system level.
Abstract: The PowerPC AS™ A10 64-bit RISC microprocessor is a 4.7-million-transistor integrated circuit design, using IBM CMOS 5L 0.5-µm, 3-V, four-level-metal ASIC technology. Support for the PowerPC AS architecture is implemented in a 213-mm 2 die using a semicustom design methodology. Chip density and speed are enhanced through the use of custom macros and multiport arrays. An on-chip phase-locked-loop circuit is used to reduce chip-to-chip clock skew. Full utilization of the four-level-metal interconnect technology was achieved through architectural floorplanning, performance clustering, and timing-driven placement and wiring, with a total wire length of over 102 meters placed on the 14.6 × 14.6-mm die. The microprocessor is a pipelined, superscalar design with five separate functional units, a 4KB instruction cache, and an 8KB data cache. The design includes parity, error-correction, and error-logging functions, as well as self-test for logic and arrays during power-on. The design is robust and implements a wide range of performance configurations at the system level, allowing direct attachment of DRAM to the processor, or high-performance L2 cache options using high-speed SRAM. An on-chip system I/O bus and bus controller are provided for attachment of peripherals.

5 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823