Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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09 Nov 2010
TL;DR: Experimental results indicate that with a relatively small degree of parallelism, corresponding to modest hardware cost, the overall frame rate can be increased between 18 and 105 % depending on processing and application parameters.
Abstract: Hardware acceleration is a popular method to boost performance in video processing applications. This paper shows how to accelerate such applications on a general-purpose CPU by means of a coprocessor that is tightly-coupled to the instruction pipeline. A method for efficient data transfer between CPU and coprocessor is developed, and the resulting data path architecture with optimum scheduling of operations is demonstrated. Based on this method, a coprocessor has been implemented in a Virtex-5 FPGA with embedded PowerPC to accelerate candidate operations of a video content analysis algorithm. Experimental results indicate that with a relatively small degree of parallelism, corresponding to modest hardware cost, the overall frame rate can be increased between 18 and 105 % depending on processing and application parameters.
5 citations
07 Dec 2001
TL;DR: It is shown that (i) a simulation model is an approximation of the corresponding abstract specification and (ii) the abstracted memory core can be composed with the un-abstracted surrounding logic using a simple theory of composition.
Abstract: We present a methodology in which the behavior of custom memories can be abstracted by a couple of artifacts-one for the interface and another for the contents. Memories consisting of several ports result into several user-provided abstract specifications, which in turn can be converted to simulation models. We show that (i) a simulation model is an approximation of the corresponding abstract specification and (ii) the abstracted memory core can be composed with the un-abstracted surrounding logic using a simple theory of composition. We make use of this methodology to verify equivalence between register transfer level and transistor level descriptions of custom memories.
5 citations
21 May 2007
TL;DR: Euler and Runge-Kutta numerical methods for Real-Time differential equations solution are presented and the performance of these methods is evaluated in the fixed step simulation of the air supply system and stack in Fuel Cell systems.
Abstract: In this paper, the need of having real-time emulators for Fuel Cells systems is described. Euler and Runge-Kutta numerical methods for Real-Time differential equations solution are presented. The performance of these methods is evaluated in the fixed step simulation of the air supply system and stack in Fuel Cell systems, looking for a system that allows to predict and emulate the Fuel Cell behavior. Finally, computational loads of the selected numerical methods are evaluated using different systems: MATLAB Real-Time Windows Target Toolbox, free-cost RTAI-Linux Target, dSpacecopy enterprice PowerPC target and a TMS320C6711 DSP Embedded System.
5 citations
Icos1
TL;DR: A watershed based segmentation algorithm on a Virtex II pro platform enabled by the embedded processor power PC with low execution time and minimal internal FPGA consumed resources is implemented.
Abstract: Watershed transformation is a powerful technique that can be efficiently used for image segmentation. In this paper, we implement a watershed based segmentation algorithm on a Virtex II pro platform. The main contribution of this work is the low execution time and minimal internal FPGA consumed resources. 'The proposed architecture includes two main blocs. First, a gradient of the image is generated using morphological operators (dilation-erosion). Then, Watershed is applied to the resultant image based on immersion principle. The proposed implementation was optimized with respect to hardware resources occupation and speed, based on a Codesign methodology. Our approach makes use of the potential software in Virtex II PRO platform enabled by the embedded processor power PC. Firstly, in a high design level, the whole design was done in PowerPC. Then, the optimal design is carried out by analyzing the timing of the different portions of the algorithm and implementing the time extensive parts as hardware This strategy leads to acceptable hardware resources occupation and a maximum frequency performance of approximately 100 MHz. As illustration, we apply our design to the segmentation of Cameraman image.
5 citations
IBM1
TL;DR: A beta test case currently in operation on IBM's latest PowerPC products in their copper and SOI technologies is described, which addresses a broad scope of issues from Product Design and Manufacturing Test, to Diagnostic and Data Analysis Tools.
Abstract: Today's industry is expanding the high performance microprocessor market into the consumer market place This market requires very low cost, high reliability, stricter SPQL levels, and very high yields A New Diagnostic Methodology is required to meet these new demands This paper addresses a broad scope of issues from Product Design and Manufacturing Test, to Diagnostic and Data Analysis Tools It describes a beta test case currently in operation on IBM's latest PowerPC products in their copper and SOI technologies
5 citations