PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Flight SEU Performance of the Single Board Computer (SBC) Utilizing Hardware Voted Commercial PowerPC Processors On-board the CALIPSO Satellite

Abstract: 603r PowerPC single board computer SEU rate predictions are compared to on-orbit CALIPSO data. Upset mitigation includes hardware voting 3 or 4 processors with transparent system upset monitoring and recovery. The 7447A PowerPC (G4) radiation performance is also reported.

Feedback scheduling for energy-efficient real-time homogeneous multiprocessor systems

Abstract: Real-time scheduling algorithms proposed in the literature are often based on worst-case estimates of task parameters and the performance of an open-loop scheme can therefore be poor. To improve on such a situation, one can instead apply a closed-loop scheme, where feedback is exploited to dynamically adjust the system parameters at run-time. We propose an optimal control framework that takes advantage of feeding back information of finished tasks to solve a real-time multiprocessor scheduling problem with uncertainty in task execution times, with the objective of minimizing the total energy consumption. Specifically, we propose a linear programming-based algorithm to solve a workload partitioning problem and adopt McNaughton's wrap around algorithm to find the task execution order. Simulation results for a PowerPC 405LP and an XScale processor illustrate that our feedback scheduling algorithm can result in an energy saving of approximately 40% compared to an open-loop method.

An FPGA-based high-speed, low-latency trigger processor for high-energy physics

Abstract: An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules and one top module. All modules contain the same PCB, FPGA, DDR SRAM and SDRAM, but are equipped with different optional components and additional interface boards, which simplifies the hardware development significantly and reduces the production costs. Embedded PowerPC processors running Linux systems are used to implement a control and monitoring system. The system was installed in the real environment in December 2007 and is in continuous operation for cosmic data taking.

Application-based, transistor-level full-chip power analysis for 700 MHz PowerPC/sup TM/ microprocessor

Abstract: A chip-level transient power analysis methodology for the 700 MHz PowerPC/sup TM/ microprocessor has been presented. Transistor-level simulation is used for best accuracy, while input vectors are gathered at the architectural level from certain applications. The IVP is used to describe the sequence of instructions that drive the applications under architecture-specific constraints. The generated cycle-based logic behaviors are then mapped to the timing-based input vectors to regenerate the timing relationship between signals. Algorithms have been presented for simulating the transient power. This methodology can simulate the blocks in a hierarchical manner, while the accuracy is preserved. By fetching the logic values from the AET file, the simulation can start at any user specified cycle to handle RTX state preload and to avoid simulation time waste at the initialization period. Three simulation cases have been studied, including a large custom array, an FPU, and the full chip including IR-drop analysis. This transient power analysis methodology has been successfully employed along the course of PowerPC/sup TM/ development for the power-aware design of the next-generation microprocessor.