PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

PCIE interface design for high-speed image storage system based on SSD

Abstract: This paper proposes and implements a standard interface of miniaturized high-speed image storage system, which combines PowerPC with FPGA and utilizes PCIE bus as the high speed switching channel. Attached to the PowerPC, mSATA interface SSD(Solid State Drive) realizes RAID3 array storage. At the same time, a high-speed real-time image compression patent IP core also can be embedded in FPGA, which is in the leading domestic level with compression rate and image quality, making that the system can record higher image data rate or achieve longer recording time. The notebook memory card buckle type design is used in the mSATA interface SSD, which make it possible to complete the replacement in 5 seconds just using single hand, thus the total length of repeated recordings is increased. MSI (Message Signaled Interrupts) interruption guarantees the stability and reliability of continuous DMA transmission. Furthermore, only through the gigabit network, the remote display, control and upload to backup function can be realized. According to an optional 25 frame/s or 30 frame/s, upload speeds can be up to more than 84 MB/s. Compared with the existing FLASH array high-speed memory systems, it has higher degree of modularity, better stability and higher efficiency on development, maintenance and upgrading. Its data access rate is up to 300MB/s, realizing the high speed image storage system miniaturization, standardization and modularization, thus it is fit for image acquisition, storage and real-time transmission to server on mobile equipment.

Development of a low cost, fault tolerant, and highly reliable command and data handling computer (Pulse/sup TM/)

Abstract: Command and data handling computers have been designed to manage the different and many remote interface units within the satellite "bus" platform. In this distributed architecture, the command and data handling requires low throughput processors (1-4 MIPS) to pass data to other units or for download to ground stations for further processing. The advent of very large radiation hardened ASICs has enabled the application of powerful processing of the RHPPc (based on the Motorola licensed PowerPC 603e) with a simplified IEEE-1394 backplane bus to provide a highly reliable and cost competitive centralized command and data handling sub-system as described. This robust architecture is tailorable and easily modified to meet the varying needs of the satellite and space transportation applications. By using a commercially compliant processor (RHPPc is fully compliant with the instruction set of PowerPc 603e processor), software and its tools, which are one of the most complex, high risk, and expensive undertakings of the system architecture for a satellite bus controller, become a low risk design issue and much more cost effective. An extensive array of Commercial Off The Shelf (COTS) software tools is currently available for the Power PC processor family, rendering the software development environment associated with the Pulse/sup TM/ to be a relatively low impact on the overall program, thus reducing the overall program recurring and non-recurring cost. Pulse/sup TM/ supports most of the COTS operating systems with the current Board Support Package (both basic and custom) being designed to be VxWorks compliant.

General-purpose microprocessor performance for DSP applications

Abstract: Digital signal processors (DSPs) have been used to realize real-time signal processing systems using hardware architectures and software instruction sets that are optimized for such applications. However, general-purpose microprocessors have risen in capability to the point that they can serve as alternative platforms for digital signal processing applications, particularly for audio-rate systems. This paper compares the capabilities of two general-purpose microprocessors-the Apple/IBM/Motorola PowerPC 604 and Intel Pentium PB-with the popular Texas Instruments' TMS320C40 DSP on a suite of three common signal processing subsystems: (i) a finite-impulse-response (FIR) filter, (ii) the least-mean-square (LMS) adaptive filter, and (iii) the fast Fourier transform (FFT). Careful attention is paid to the architectures of the processors to obtain the most computationally-efficient realizations. The results indicate that general-purpose microprocessors are viable computational engines for audio-rate processing.

Low-power consumption and high-performance processing module and construction method thereof

Abstract: The invention proposes a low-power consumption and high-performance processing module and a construction method thereof. The processing module is a POWERPC low-power consumption P series or T series dual-core or four-core processor, two processors are arranged, the processing performance of the processor is larger or equal to 9.2GIPS, a dynamic random-access memory (RAM) storage, a FLASH storage and an nvRAM storage are configured in each processor, a network communication interface is arranged in the processing module and is implemented by adopting a system on chip (SOC), the network data is exchanged with the dynamic RAM storage through a direct memory access (DMA) mode, a programmable control logic unit is arranged in the processing module and adopts a complex programmable logic device (CPLD) chip, a processor working frequency register and a FLASH storage enable register are arranged, and processing module working condition monitoring and processing module fault management and control are arranged. The invention provides the low-power consumption and high-performance processing module, the module reliability is improved by substantially reducing the power consumption of the module, meanwhile, the module is more universal, and the application environment and the application field of the module are expanded.

Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture

Abstract: The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x---13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.