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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
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Proceedings ArticleDOI
12 Aug 2010
TL;DR: A FPGA-based framework is presented that is designed and implemented on a Virtex 4 that can be used to compute Stillinger-Weber potential and extends the PowerPC instruction set to include vector operations and a custom datapath.
Abstract: The computer simulation of three-body potentials using the Stillinger-Weber method has been extensively used in the study of three-body molecular forces between partially rigid molecules such as silicon. The Stillinger-Weber method of computing three-body interactions is generally computationally intense. This paper presents a FPGA-based framework that is designed and implemented on a Virtex 4 that can be used to compute Stillinger-Weber potential. This framework extends the PowerPC instruction set to include vector operations and a custom datapath. Design details of the framework along with initial performance results with two well-known data sets are also presented. The results show that FPGA design is competitive with current microprocessors on small problems sizes and with only half of the algorithm implemented. As the problem size increases, the results suggest the FPGA-based design will gain a significant performance advantage. Coding the second half of the algorithm will increase the on-chip parallelism as well.

4 citations

01 Jan 2003
TL;DR: Details of the design and implementation of a 64-bit PowerPC Port and of the requirements for the Degree of Master of Science Computer Science are presented.
Abstract: OF THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Computer Science The University of New Mexico Albuquerque, New Mexico December, 2003 Jikes Research Virtual Machine Design and Implementation of a 64-bit PowerPC Port

4 citations

Proceedings ArticleDOI
01 Sep 1997
TL;DR: The architecture and development of an innovative memory controller for the PowerPC family, HiBRIC-MEM (High Bandwidth Resource Interface Controller), which provides control for up to two PowerPC processors is described.
Abstract: This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 /spl mu/m, three metal layer Motorola technology and has a die size of 12.1/spl times/12.1 mm/sup 2/. HiBRIC-MEM is used, for example, in a commercially available parallel computer.

4 citations

Proceedings ArticleDOI
M. Gruver1, N. Phan1, T. Aipperspach1, S. Hilker1, J. Bartley1 
10 Oct 1994
TL;DR: This paper describes the technology and semi-custom design aspects of the AS/400 PowerPC chip set, which was designed and packaged in a multi-chip, high performance package to form the processor engine.
Abstract: This paper describes the technology and semi-custom design aspects of the AS/400 PowerPC chip set. In order to meet the growing demand for AS/400 system performance, a 6 ns cycle time was specified. This requirement, coupled with the desire for a short development cycle, drove the chip team to choose a semi-custom design style utilizing a mature BICMOS technology. Three semi-custom chips and one ASIC were designed and packaged in a multi-chip, high performance package to form the processor engine. >

4 citations

Proceedings ArticleDOI
22 Jun 2006
TL;DR: The paper presents the application of the modified real-time Linux kernel as the operating system for the computational node of CCM (custom computing machine) class parallel system designed to aid the simulations of three-dimensional electromagnetic field.
Abstract: The paper presents the application of the modified real-time Linux kernel as the operating system for the computational node of CCM (custom computing machine) class parallel system designed to aid the simulations of three-dimensional electromagnetic field. The computational node is the application-specific design optimized for the implementation in the FPGA. It is based on Xilnx VirtexIIPro FPGA equipped with two embedded cores of the PowerPC processors. The presented real-time kernel is designed to run on one of the cores. The paper details the procedure needed to create the kernel customized for the specific architecture of the system. The software packages and tools utilized in the kernel development process are also presented

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823