PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

An embedded architecture for implementation of a video acquisition module of a smart camera system

Abstract: This paper presents an embedded architecture for real-time video acquisition module which is a vital part of a smart camera system. The Xilinx ML-507 platform has been used to develop the proposed embedded architecture. Apart from the required necessary peripherals, the platform contains a Virtex-5 FX FPGA device having PowerPC 440 processor embedded in the FPGA fabric itself. In order to develop the required hardware and software in an integrated fashion, Xilinx Embedded Development Kit (EDK) design tool has been used. A number of Xilinx provided IPs are customized to realize the hardware modules in the FPGA fabric. To implement the real-time video capture and display functionality for the smart camera system, a Pan-Tilt-Zoom (PTZ) camera and a VGA monitor have been interfaced with the platform. This interfacing uses on-board VGA input video codec and DVI transmitter chips. The control registers of these chips are configured using the embedded PowerPC 440 processor with Inter-Integrated Circuit (IIC) bus controller's low-level device driver functions. The application software, written in C language, runs on top of a standalone software platform and uses the application programmer interface (API) provided by the software platform. The device utilization summary shows that, with the proposed embedded architecture based video acquisition module, the remaining FPGA resources are sufficient for implementing any reasonably complex real-time video processing application.

PowerPC-based system for tracking in infrared image sequences

Abstract: Tracking deformable objects is very important in many applications such as surveillance, security and military. In this paper, we implement one tracking scheme based on the block matching using PowerPC. We implement tracking algorithm using information from Infrared (IR) sensor for object tracking. When an occlusion occurs, the proposed algorithm predicts movements of an object using the historical tracking information and it can keep the object tracking. Based on experimental results, the proposed system can reduce calculation time and track object under condition of camera jitter and the occlusions.

CGaAs PowerPC FXU

Abstract: The development of a PowerPC™ fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola's 0.5—µm Complementary Gallium Arsenide process, the device operates from 0.9 to 1.9 V with a nominal frequency of 25 MHz at 1.3 V, dissipating 274 mW.

Hardware and software optimization of fourier transform infrared spectrometry on hybrid-FPGAs

Abstract: With the increasing complexity of today’s spacecrafts, there exists a concern that the on-board flight computer may be overburdened with various processing tasks. Currently available processors used by NASA are struggling to meet the requirements of scientific experiments [1, 2]. A new computational platform will soon be needed to contend with the increasing demands of future space missions. Recently developed hybrid field-programmable gate arrays (FPGA) offer the versatility of running diverse software applications on embedded processors while at the same time taking advantage of reconfigurable hardware resources, all on the same chip package. These tightly coupled HW/SW systems consume less power than general-purpose singleboard computers (SBC) and promise breakthrough performance previously impossible with traditional processors and reconfigurable devices. This thesis takes an existing floating-point intensive data processing algorithm, used for on-board spacecraft Fourier transform infrared (FTIR) spectrometry, ports it into the embedded PowerPC 405 (PPC405) processor, and evaluates system performance after applying different hardware and software optimizations and architectural configurations of the hybrid-FPGA. The hardware optimizations include Xilinx’s floating-point unit (FPU) for efficient single-precision floating-point calculations and a dedicated single-precision dot-product co-processor assembled from basic floating-point operator cores. The software optimizations include utilizing a non-ANSI single-precision math library as well as IBM’s PowerPC performance libraries recompiled for double-precision arithmetic only. The outcome of this thesis is a fully functional, optimized FTIR spectrometry algorithm implemented on a hybrid-FPGA. The computational and power performance of this system is evaluated and compared to a general-purpose SBC currently used for spacecraft data processing. Suggestions for future work, including a dual-processor concept, are given.

Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

Abstract: The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.