PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

An investigation of the performance of various instruction-issue buffer topologies

Abstract: In out-of-order issue superscalar microprocessors, instructions must be buffered before they are issued. This buffer can be either unified (one buffer linked to all functional units) as in the P6, distributed among the units as in the PowerPC 620, or semi-unified (a few buffers each shared by several units) as in the MIPS R10000. Of course, the size of this buffer also plays a leading role in the performance of the processor. Intensive trace-driven simulations on the SPEC92 suite have been made in order to determine the best designs and relevant choices are pointed out according to the dispatch width of the processor.

Performance and power evaluation of an in-line accelerator

Abstract: In this paper we evaluate the performance and power of a processor-attached in-line accelerator. The accelerator provides high-performance SIMD computing and power efficiency by means of a very large register file and a set of vector multimedia extensions based on IBM's PowerPC VMX. Our experiments show significant performance improvements and power reduction, compared to a baseline vector execution unit, mainly due to the drastic decrease of memory accesses caused by the software-managed locality of the very large register file. Total execution time is, on average, reduced by 61%, while consuming 55% less energy.

Comparing the Parix and PVM parallel programming environments

Abstract: Genericity of parallel programming environments, enabling development of portable parallel programs, is expected to result in performance penalties. Furthermore, programmability and tool support of programming environments are important issues if a choice between programming environments has to be made. We propose a methodology to compare native and generic parallel programming environments, taking into account such competing issues as portability and performance. As a case study, this paper compares the Parix and PVM parallel programming environments on a 512 node Parsytec GCel. Furthermore, we apply our methodology to compare Parix and PVM on a new architecture, a 32 node Parsytec PowerXplorer, which is based on the PowerPC chip. In our approach we start with a representative application and isolate the basic (environment) dependent building blocks. These basic building blocks, which depend on floating point performance and communication capabilities of the environments, are analysed independently. We have measured point to point communication times, global communication times and floating point performance. All information is combined into a time complexity analysis, allowing the comparison of the environments on different degrees of functionality.

A Translator from CRL2 representation of PowerPC Assembly to ALF

Abstract: Real Time systems are systems which must give accurate results within a precise time period. These systems have now become an indispensable aspect of our day to day lives. As the importance of real ...

Efficient sub-pixel interpolation and low power VLSI architecture for fractional motion estimation in H.264/AVC

Abstract: In this paper we propose an efficient, low power algorithm and its co-designed VLSI architecture for fractional-pel motion estimation (FME) in H.264/AVC. Our fractional-pel motion estimator uses a simplified FIR filter for half-pel interpolation. Usage of this filter reduces the required number of computations and the memory size and bandwidth for half-pel interpolation. Our simulations compare our algorithm with the state-of-the-art, in terms of rate-distortion performance and computational complexity. Our VLSI architecture is prototyped on a Field Programmable System on Chip (FPSoC), comprising a Virtex-II Pro FPGA and an embedded PowerPC processor. Our results show that our algorithm on average has better rate-distortion performance, compared to previous state-of-the-art FME algorithms, while its losses compared to FME in H.264/AVC, are insignificant. Our prototyped architecture is more hardware-efficient than previous FPGA-based architectures, in terms of power consumption, throughput, area and memory utilization. We also show that its performance in terms of transistor count, throughput and power consumption, are comparable to that of state-of-the-art ASIC implementations.