PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

A scalable performance analysis tool for PowerPC based MPP systems

Abstract: This paper introduces a tool for optimizing programs on massively parallel computing systems. The tool has been implemented for a PowerPC based parallel computing platform. It is scalable with respect to its implementation and an the way it presents performance data. A major feature contributing to the scalable representation of performance data is the ability to focus measurements on points of interest in the program execution by specifying behavioral attributes. Behavioral attributes are given as thresholds to the results of other measurements. Thus a direct link between results of different measurements can be made which enables the user to link global system behavior to the execution of individual program parts. >

Just-in-Time Instruction Set Extension - Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture

Abstract: In this paper, we study the feasibility of moving the instruction set customization process for reconfigurable ASIPs to runtime under the precondition that current FPGA devices and tools are used. To this end we propose a tool flow for just-in-time ASIP customization which identifies suitable custom instructions to accelerate arbitrary binary applications that execute on a virtual machine. The tool flow targets our previously introduced Woolcano reconfigurable ASIP architecture, which augments the PowerPC core in a Xilinx Virtex 4FX CPU with runtime reconfigurable instructions. % We evaluate the tool flow with a comprehensive set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites and compare the speedups that can be achieved with the overhead of the complete ASIP specialization process. % We show that an average speedup of $5times$ can be achieved for benchmarks from the embedded computing domain. The overhead of custom instruction identification and hardware generation for these benchmarks is less than 50 minutes and will be compensated if the applications execute for more than 2 hours. Finally, we evaluate caching strategies to reduce the time until this break even point is reached.

A Pthreads-Based MPI-1 Implementation for MMU-Less Machines

Abstract: AzequiaMPI is a new thread-based full conformant implementation of the MPI-1 standard for MMU-less processors. It runs on a Linux desktop and on the entire Texas Instruments TMS320C6000 family of digital signal processors, as well as on MicroBlaze and PowerPC 405, which makes AzequiaMPI a useful tool in the reconfigurable MPSoC arena. AzequiaMPI needs a Pthreads box, what in most cases means the support of an underlying operating system as Xilkernel or uClinux. This paper discusses design issues and gives memory footprint and performance figures in a Xilkernel/PowerPC405 Xilinx FPGA.