Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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IBM1
TL;DR: The hardware and software design processes used in the product development, as well as performance results obtained on the first-generation PowerPC 601-based hardware are described.
Abstract: The first PowerPC-based SMP jointly developed by IBM and Croup Bull, had aggressive performance goals for its intended market of commercial applications. This paper describes the hardware and software design processes used in the product development, as well as performance results obtained on the first-generation PowerPC 601-based hardware.
3 citations
07 Oct 1996
TL;DR: A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 /spl mu/m, CMOS technology is described and simulation and characterization results show the response of the PLL to power supply and input clock modulation.
Abstract: A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 /spl mu/m, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results show the response of the PLL to power supply and input clock modulation.
3 citations
01 Jan 2009
TL;DR: The detail of the design and the implementation, as well as the experiences of the system in the operation of the J-PARC MR, are described.
Abstract: There are the 4 output beam lines at the Main Ring(MR) in J-PARC. The Accelerator protection system (MR-MPS) watches the devices which deal with destination of the beam. Then, the complicated logic judgment carries out using FPGA (Virtex-4 FX). On PowerPC core in the FPGA, LINUX+EPICS is operated. Though there are both logic processing unit and CPU on one element, the information transfer in high speed between logic processing part and CPU is possible without requiring the complicated external wiring. In this reason, the system can be very efficiently constructed. This paper describes the detail of the design and the implementation, as well as the experiences of the system in the operation of the J-PARC MR.
3 citations
09 Aug 2012
TL;DR: This paper presents the design method for developing a recording application for time varying data displayed on the monitor based on embedded Linux using Qt, a powerful development toolkit and results indicated that this system is working stably and reliably.
Abstract: This paper presents the design method for developing a recording application for time varying data displayed on the monitor based on embedded Linux using Qt, a powerful development toolkit. Recording of the visualization of time varying data to video is perceived to be a convenient and easy-to-use solution for the intense data analysis anywhere/anytime. The application is based on IBM's PowerPC 7410, while the software platform is Embedded Linux and the development environment features are Qt and Qt/Embedded. The embedded operating system is MontaVista Linux with X11 built as an abstract layer on kernel providing graphics capability to the system. The open source FFmpeg library is employed to encode captured window frames to mpeg video. The experimental testing and results indicated that this system is working stably and reliably. The implementation of the entire design environment is based on the X Window System and the Linux operating system and can thus be used on an increasing number of low-cost workstations.
3 citations
16 Jul 2008
TL;DR: This paper describes an implementation of spatial domain filtering which have been re-architected for implementation on the cell broadband engine and the results are compared with the performance of the algorithm on conventional platforms.
Abstract: The cell broadband engine architecture (CBEA) is a nine-core architecture, including a 64-bit powerPC processor element (PPE) and eight synergistic processor elements (SPE) which offers a raw compute power of up to 200 GFlops per 3.2 GHz chip. The cell bears a huge potential for compute intensive applications but also requires addressing the challenges caused by this processorpsilas unconventional architecture. In this paper we describe an implementation of spatial domain filtering which have been re-architected for implementation on the cell broadband engine. The results are compared with the performance of the algorithm on conventional platforms. In addition we show our measurements and speed-up.
3 citations