PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

High-power wind-power conversion system based on EtherCAT communication

Abstract: The invention provides a high-power wind-power conversion system based on EtherCAT communication. The high-power wind-power conversion system comprises a core control CPU (Central Processing Unit) and at least one power unit, wherein the core control CPU is a powerPC processor; and each power unit comprises a signal acquisition unit, a core computing unit, a PWM (Pulse-Width Modulation) unit, a driving unit and an output unit which are in a signal connection in sequence. The high-power wind-power conversion system based on the EtherCAT communication has the beneficial effects that the power units and control cores are modularized, and an EtherCAT internal bus is adopted, so that the probability in implementation of wind-power converters of different capacities is increased greatly; different application demands in the industry can be met truly through one-time development; a good development platform is provided for secondary development of other systems; the development periods of new products are greatly shortened; and the manpower and material resource cost is reduced at the same time.

Hardware device and method for assisting in processing dynamic bandwidth allocation algorithm

Abstract: The invention discloses a hardware device and a method for assisting in processing a dynamic bandwidth allocation (DBA) algorithm. The hardware device comprises a hardware logic module, a register interface control module, a synchronous dynamic RAM controller module, a FLASH controller module, an interrupt processor module, a universal asynchronous receiver/transmitter controller module, and a master-slave communication module, a master-slave communication interface module, a PowerPc CPU module, a processor bus module, a processor bus-to-on-chip- peripheral-bus bridge module and an on chip peripheral bus module which are orderly connected, wherein the PowerPc CPU module is used for processing and controlling data acquired by the hardware logic module, is connected with a master CPU interface in the hardware logic module through the master-slave communication module to finish communications between an embedded CPU and a master CPU, and controls and configures a register in the hardwarelogic module and the report and the allocation of the dynamic bandwidth allocation algorithm through a register interface module. The hardware device and the method for assisting in processing the dynamic bandwidth allocation algorithm can flexibly process the DBA core algorithm and save the cost.

Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo

Abstract: This paper describes the approach used to model the memory circuits contained in the Gekko microprocessor and the delay testing that was done at functional speeds using these models. The combination of accurate memory models and good delay testing has produced a tenfold reduction in customer returns for this chip compared with prior PowerPC programs.

Method for updating PowerPC motherboard guide chip online

Abstract: The invention provides a method for updating a PowerPC motherboard guide chip online. The method comprises the following steps: electrifying the system, and maintaining an update flag bit by a programmable logic device FPGA; transmitting a bootrom mirror image file to the system by an upper computer through a serial port in an update flow, and receiving and checking whether mirror image contents are correct by an update program; writing the checked mirror image contents in an FPGA operable address space, writing the mirror image contents in a working area by the FPGA, and meanwhile backing up the current mirror image; and starting the system again to accomplish the present update in the system, and otherwise rolling back the backup data in a backup area.

Is state mapping essential for equivalence checking custom memories in scan-based designs?

Abstract: Equivalence checking between Register Transfer Level (RTL) descriptions and transistor level descriptions of custom memories is an important step in the design flow of high performance microprocessors. Equivalence checking can be done with or without the knowledge of state mapping between the two descriptions. We present evidence that because of state mapping, our verification technique exercises system behavior that exposes hard-to-detect bugs that might otherwise go undetected. This paper defines Crossover Bugs (CB's) that can be present in scan-based custom designs and that are inherently hard-to-detect without state mapping. We demonstrate that such bugs can be missed by equivalence checking techniques that do not have state mappings between the two descriptions. By identifying the state correspondences between the RTL and the transistor implementation of custom memories, a more rigorous equivalence check can be performed compared to traditional equivalence checking methods such as product machine constructions. We also compare the time and memory complexities of crossover bug detection capability of the two equivalence checking approaches. We conclude with experimental results of CB detection on some of the custom designed embedded memories of Motorola's MPC 7455 microprocessor (compliant with IBM's PowerPC instruction set architecture).