PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Development of BGA solution for the IBM PowerPC 970 module in Apple's Power Mac G5

Abstract: Apple's Power Mac G5 systems use either one or two IBM PowerPC 970 chips. Initial systems built with the PowerPC 970 64-bit processor run at speeds up to 2.0 GHz. These chips are packaged on IBM ceramic BGA (ball grid array) modules. The high performance modules dissipate high power, which presents new packaging challenges. One of these challenges has been addressed successfully by improving the thermo-mechanical integrity of the solder interconnections between the chip carrier module and the organic processor board. The PowerPC 970 chip dissipates high power in a small area and is aggressively cooled using a state-of-the art heatsink design. This paper describes how through a cooperative effort between Apple and IBM, a BGA reliability enhancement was evaluated and successfully implemented. Use of BGA underfill strengthens the BGA connections between the processor module and the processor card and increases long term reliability performance affected by creep and cyclic fatigue.

Implementing FORTRAN77 support in the GNU gdb debugger

Abstract: Commercially available source-level debuggers in the Unix world often shortchange FORTRAN77 users. While C and C++ are usually well-supported languages, FORTRAN77 has not been given the attention it deserves. Given the current interest in performance-measurement via the popular SPEC benchmarks (many of which are coded in FORTRAN77) as well as the large installed-base of mathematical/scientific FORTRAN77 software, it is imperative for system software vendors to provide FORTRAN77 users with the same sort of fast, effective and powerful source-level debugging environment that C and C++ users enjoy. This paper details the addition of FORTRAN77 features to the GNU gdb[2] debugger in order to better support users of the highly-optimizing Motorola PowerPC1 mf77 compiler. These FORTRAN77 features currently (as of version 4.10) only target the native PowerPC mf77 compiler distributed by Motorola.

3D-brain 2.0--narrowing the gap between personal computers and high end workstations.

Abstract: UNLABELLED Recent advances in personal computer hardware and software have pushed the graphic capacity of these easier to use and, more importantly, cheaper computers to a level approximating the current standard of high end workstations. The interactivity and graphic complexity of a modern PC is rapidly approaching the current standard on Silicon Graphics (although with respect to texture mapping, the SGI is still ahead of the PCs). The modern medical student laboring under increasingly higher demands with respect to versatility, not only in basic science and traditional medical knowledge, is also faced with the requirement to learn and understand modern scientific visualization and analytical instruments. Furthermore, basic knowledge of information technology and computer literacy is expected of the next generation medical professionals. These demands forces medical schools to increasingly invest in computers and information technology for educational purposes. Due to common class sizes, these computers are most commonly Windows PCs or Apple Macintoshes. For distance education, telematics or studies at home, personal computer versions of the workstation graphics are a necessity. 3D-Brain 2.0 is an educational software package intended to run on basic personal computers and utilizing modern software technologies such as QuickTime VR 2.0 and VRML 2.0, to provide the students with insight into modern clinical and scientific visualization, focusing on the anatomy and functionality of the human brain. The aim of this paper to test the validity and usefulness of these new visualization techniques. METHODS 3D-Brain is based on human brains sliced in 1 mm sections (NB. NOT based on NLMs Visual Human). Each slice was photographed, digitized, optimized and aligned using proprietary software. The datasets were then created by manual tracing followed by triangulation, smoothing and 3D visualization using Silicon Graphics computers. For the QuickTime VR project, 684 images with a 10 degrees angle were generated for each scene and ported to an Apple Macintosh computer for further manipulation. VRML code was generated directly from the original dataset. All interactivity was programmed on a Macintosh and subsequently ported to the Windows95 PC platform. The minimum requirements to run the software are either a PowerPC based Macintosh computer or a Pentium based Windows 95 computer with 16 Mb, 16 bit display and a 4 speed CD-ROM. RESULTS AND DISCUSSION 3D-Brain 2.0 provides medical students at Goteborg University the means to complement traditional teaching using visualization techniques and three-dimensional models. These techniques also serve as an insight into the different clinical means of visualization the student will encounter throughout his/her continued education and professional career. For educational purposes, it has been established that among the tested new visualization techniques, CD-ROM based software utilizing QTVR is still the best methodology to use for pedagogical software. VRML shows promise in porting these software packages to the Web while Open Inventor is the preferred format for research purposes.

An Investigation Of Power Delay Trade-offs On Powerpc

Abstract: Logic and structural transformations to reduce power have been considered by a number of authors. [Z, 3, 4 , 51. However, all the results presented so f a r have been based o n models of power and estimation methods that may not be a accurate reflection of ‘real world’ constraints. The performance requirements of industrial designs often significantly restrict the applicability of the power reducing transformations. I n this paper we present the results of investigations o n the e f i cacy of a recently reported logic level power optimizing algor i thm [5] o n some commercial circuits, using customer supplied input waveforms. Based on a accurate delay model, the power consumption of the circuits is estimated using the commercial package called ‘PowerMill’. The experimental results show that a maxamum 21 % average power and 27.7% peak power power reduction can be obtained with only 3% delay increase. Based on the experiments, we propose a general methodology f o r the practical application of the transformations for power optimization of CMOS logic circuits. Finally, a comparison between the experiments using random input waveforms and customer provided input waveforms is presented.