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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
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01 Jan 2007
TL;DR: The controlling methods of general purpose of I/O(GPIO) in the embedded system are introduced and the methods in the core level and in the Linux by the analysis of the start process of Linux are gotten.
Abstract: The controlling methods of general purpose of I/O(GPIO) in the embedded system are introducedThe methods in the core level by the analysis of the GPIO of PowerPC 8248 and in the Linux by the analysis of the start process of Linux are gottenThe platfom researched is based on the PowerPC 8248 embedded systemThe system environment is Linux system

2 citations

Patent
09 Mar 2018
TL;DR: In this article, a communication method between an FPGA and a PC on the basis of a PowerPC and a network port is presented, where PowerPC control is not needed in the data transmission process, and an external module is used for controlling.
Abstract: The invention discloses a communication method between an FPGA and a PC on the basis of a PowerPC and a network port. By means of the method, PowerPC control is not needed in the data transmission process, and an external module is used for controlling. When data is written into an RAM, the external module notifies the PowerPC to process the data through triggered interruption; when the PowerPC needs to transmit the data to a function module, a rising edge is provided for the function module through a GPIO port, and the function module is informed of reading the data. By means of the method, the time expenditure in the data receiving, storing and sending processes is greatly reduced for the PowerPC, and the possibility of communication collapse can be effectively reduced on occasions withhigh instantaneity requirements.

2 citations

Proceedings ArticleDOI
22 Apr 2003
TL;DR: A software framework for the parallel execution of sequential programs using C++ classes is presented, which promises a composable multi paradigm, unified approach to parallelism across different technologies: PowerPC, DSP and FPGA.
Abstract: A software framework for the parallel execution of sequential programs using C++ classes is presented. The functional language Concurrent ML is used to implement the underlying harness and to design the programming interfaces. The hardware-independent harness promises a composable multi paradigm, unified approach to parallelism across different technologies: PowerPC, DSP and FPGA. Performance results for an image processing case study are given.

2 citations

Proceedings ArticleDOI
24 Aug 2009
TL;DR: This paper presents a light weight, simplified prototype of a Sensor Processing Unit (SPU) that offloads these computations from the main Arithmetic Logic Unit (ALU) of an embedded processor, and that accesses sensor data in a low latency manner.
Abstract: Sensor processing is a common task within many embedded system domains, such as in control systems, the sensor feedback is used for actuator control. In this paper we have surveyed several embedded system domains, and extracted kernels of computation that are common across applications within a given domain, or across domains. We have shown that adding architectural support for executing these common kernels of computation can yield an overall better system performance. We present a light weight, simplified prototype of a Sensor Processing Unit (SPU) that offloads these computations from the main Arithmetic Logic Unit (ALU) of an embedded processor, and that accesses sensor data in a low latency manner. Our SPU prototype shows an average speed up factor of 2.48 over executing these kernels on an embedded PowerPC processor. A large portion of this speed up is due to our low latency method for accessing sensor data. Isolating our speed up to purely computation still shows an average speed up factor of 1.38 for these kernels.

2 citations

Proceedings ArticleDOI
TL;DR: In this article, the preliminary architecture of instrument control unit (ICU) is described, which is aimed at operating all X-ray Integral Field Unit (X-IFU) subsystems, as well as at implementing the main functional interfaces of the instrument with the S/C control unit.
Abstract: Athena is one of L-class missions selected in the ESA Cosmic Vision 2015-2025 program for the science theme of the Hot and Energetic Universe. The Athena model payload includes the X-ray Integral Field Unit (X-IFU), an advanced actively shielded X-ray microcalorimeter spectrometer for high spectral resolution imaging, utilizing cooled Transition Edge Sensors. This paper describes the preliminary architecture of Instrument Control Unit (ICU), which is aimed at operating all XIFU’s subsystems, as well as at implementing the main functional interfaces of the instrument with the S/C control unit. The ICU functions include the TC/TM management with S/C, science data formatting and transmission to S/C Mass Memory, housekeeping data handling, time distribution for synchronous operations and the management of the X-IFU components (i.e. CryoCoolers, Filter Wheel, Detector Readout Electronics Event Processor, Power Distribution Unit). ICU functions baseline implementation for the phase-A study foresees the usage of standard and Space-qualified components from the heritage of past and current space missions (e.g. Gaia, Euclid), which currently encompasses Leon2/Leon3 based CPU board and standard Space-qualified interfaces for the exchange commands and data between ICU and X-IFU subsystems. Alternative architecture, arranged around a powerful PowerPC-based CPU, is also briefly presented, with the aim of endowing the system with enhanced hardware resources and processing power capability, for the handling of control and science data processing tasks not defined yet at this stage of the mission study.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823