PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Design and test of the PowerPC 603 microprocessor

Abstract: The PowerPC 603 microprocessor is a powerful low-cost implementation of the PowerPC architecture specification. The structured design, logic verification and test data generation methodologies of the 603 are presented in this paper. The success of these methodologies has been demonstrated by meeting the 603's aggressive time-to-market goals. >

Architectural approaches for dynamic translation and reconfiguration

Abstract: A microprocessor taxonomy is introduced based on whether: (1) the hardware is static or reconfigurable and (2) the code translation process is static or dynamic. The IBM DAISY and Transmeta Crusoe/spl trade/ microprocessors are reviewed. These static hardware microprocessors support a dynamic translation process to execute programs originally compiled for the PowerPC and Intel/spl reg/ X86 microprocessors, respectively. Inspired by features from both the DAISY and Crusoe/spl trade/ microprocessors, a conceptual design of a dynamically reconfigurable microprocessor is given. Driven by the results of a preliminary study, a specific approach to designing a reconfigurable microprocessor is presented. As a part of this approach, the concept of partitioning the instruction set of a microprocessor in order to support an application, instead of partitioning the functionality of the application, is developed.

On-chip ego-motion estimation based on optical flow

Abstract: A novel system on chip (SoC) is presented for estimating the ego-motion of the vehicle based on optical flow cues. The main novelty of the system consists in its implementation as an on-chip hybrid hardware/ software system. The improvements in the FPGA technology allows to have programmable logic resources accompanied by processors on the same chip. In this way, inherently sequential tasks are implemented as software modules executed in embedded general purpose processors while hardware friendly modules are implemented in specific purpose co-processing engines. The proposed SoC is capable of estimating egomotion by using the PowerPC available in the FPGA XC4VFX60-10 of Xilinx.

Optimizing code‐copying JIT compilers for virtual stack machines

Abstract: Just-in-time (JIT) compilers are widely used to implement stack-based virtual machines, such as the Java and .NET virtual machines. One disadvantage of most JIT compilers is that they are unportable; much of the back-end is specific to the target machine. An alternative to machine-specific code generation methods is to define a routine in a high-level language for each virtual machine instruction. These can be compiled to native code using a normal C compiler. The native code for these routines can then be strung together, allowing very simple, unoptimized code to be produced just in time. In this paper we present such a system based on an existing implementation of the Forth language. We present a novel system of optimizations for the system based on exploiting common sequences of virtual machine instructions. We use a small domain specific language and tool to generate stack-optimized code for sequences of virtual machine instructions, and for choosing the most useful sequences for a code-copying compiler. By measuring the length of the resulting executable code, we allow machine-specific sequences to be chosen without any machine-dependent code in our system. Experimental results show that best (average) speedups of 47.2% (15.75%) are possible on a Pentium 4 machine, and even higher an a PowerPC based machine. Furthermore, our optimizations allow the size of the generated code to be reduced by an average of 17.9% on the Pentium 4, and 20.5% on the PowerPC over a wide range of programs. Copyright © 2006 John Wiley & Sons, Ltd.

Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer

Abstract: The utility model discloses a switching system for realizing an industry standard architecture (ISA) bus on a performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer. The switching system comprises a peripheral component interconnect (PCI) Target bridge, an ISA bus converter bridge, a direct memory access (DMA) controller and a PCI Master bridge, wherein one end of the PCI Target bridge is connected with a PCI bus and the other end of the PCI Target bridge is connected with the ISA bus converter bridge; the other end of the ISA bus converter bridge is connected with the ISA bus; one end of the PCI Master bridge is connected with the PCI bus and the other end of the PCI Master bridge is connected with the DMA controller; and the other end of the DMA controller is connected with the ISA bus. By the switching system, the problem that the PCI bus of a PowerPC computer operates external equipment in a standard ISA bus mode is solved, and the external equipment communicates with the PowerPC computer in a DMA transmission mode of the standard ISA bus.