scispace - formally typeset
Search or ask a question
Topic

PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
More filters
Journal Article
TL;DR: The feasibility of radar general processing by using general processor instead of DSP is proved through SAR real-time image processing and performance evaluation in this paper.
Abstract: A high performance radar general processor is presented in this paperIt uses 4 chips of PowerPC as its central processor and the VPX bus standard is adopted,which meets the requirements of generalization,serialization and standardizationThe applications of PowerPC general processor and RapidIO high speed serial interface enable the processor to have strong processing capability and data exchange capability,excellent universality,reconfigurability and expansibilityThe processor chooses VxWorks operation system and VSIPL math library to improve the efficiency of software developmentFinally,the feasibility of radar general processing by using general processor instead of DSP is proved through SAR real-time image processing and performance evaluation in this paper

2 citations

Proceedings ArticleDOI
16 Mar 2015
TL;DR: A HLS based design flow for Hardware/Software architecture on top of Catapult C Synthesis is proposed and the effectiveness of this approach is illustrated on the practical implementation example of a full H264/AVC video compression decoder.
Abstract: Mixed Hardware/Software architectures are often attractive solutions for Embedded System especially for real time applications. However, when the complexity of hardware functions grows, hand coding at Register-Transfer Level (RTL), which is already low and error prone, adds debugging and verification overheads that impact severely the time and costs of development. Therefore, High Level Synthesis (HLS) brings a solution to decrease the design time of dedicated hardware and keep the high abstraction level of software development. In this context we propose a HLS based design flow for Hardware/Software architecture on top of Catapult C Synthesis. We illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC video compression decoder. The hardware accelerator is the CAVLD module that takes 14% from the decoder execution time. Three architectures are presented for this module. The best one offers 85% of gain compared to software execution. The proposed architectures are implemented on a Xilinx FPGA-embedded systems prototyping board considering the PowerPC processor and a PLB bus for data communications with the CAVLC accelerator.

2 citations

Proceedings ArticleDOI
16 May 2009
TL;DR: This paper performs binary to C translation to generate the processor simulator, which can be used both for software performance evaluation or hardware performance evaluation, such as MPSoC.
Abstract: This Paper presents the realization of a simple but efficient technique to increase the performance of the processor simulator, which can be used both for software performance evaluation or hardware performance evaluation, such as MPSoC. Due to the fast increasing of the software complexity, it brings forward more requirements on the speed of the processor simulation, which simulates a certain target processor (such as PowerPC, ARM etc.) on certain host platform (usually PC ). The performance improvement of a processor simulator can enlarge the exploration space and shorten the time-to-market. The existing approaches use either interpretive simulator or complied simulator or a binary translator. This paper performs binary to C translation to generate the processor simulator.

2 citations

Patent
19 Jun 2013
TL;DR: In this paper, a data transmission remote control system based on a double-port RAM, which comprises a PowerPC processor and a second microprocessor, is presented, where the second micro processor is connected with a remote control module of a host computer via a CAN bus, and the doubleport RAM is connected between the first/second microprocessor and the PCI bus interface.
Abstract: The utility model discloses a data transmission remote control system based on a double-port RAM, which comprises a PowerPC processor and a second microprocessor. A first microprocessor, the second microprocessor and the PowerPC processor are connected with each other via a PCI bus interface, the second microprocessor is connected with a remote control module of a host computer via a CAN bus, and the double-port RAM is connected between the first/second microprocessor and the PCI bus interface. According to the utility model, division of different processors is clear, processing is fast, and processing capability is strong, thereby solving the problem that processing capability of a single processor is insufficient, realizing data exchange among multiple processors via PCI buses, and greatly improving processing capability and transmission speed among the processors.

2 citations

Proceedings ArticleDOI
R. DuPont1, D. Bearden1, R. Bailey, P. Rossbach
15 Feb 1995
TL;DR: The alliance of Apple, IBM and Motorola was formed with the vision of designing a microprocessor family able to span the scope of systems from microcontrollers to supercomputers with a common instruction set architecture and able to run common applications on all of the systems built using these processors.
Abstract: The alliance of Apple, IBM and Motorola was formed with the vision of designing a microprocessor family able to span the scope of systems from microcontrollers to supercomputers with a common instruction set architecture and able to run common applications on all of the systems built using these processors The result was the PowerPC Architecture, a third-generation RISC architecture optimized for the diverse computing requirements of the future The Somerset Design Center was set up with the mission to jointly develop microprocessors based on the PowerPC Architecture

1 citations


Network Information
Related Topics (5)
Scalability
50.9K papers, 931.6K citations
77% related
CMOS
81.3K papers, 1.1M citations
77% related
Software
130.5K papers, 2M citations
77% related
Integrated circuit
82.7K papers, 1M citations
76% related
Cache
59.1K papers, 976.6K citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823