PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

The making of the PowerPC microprocessor

Abstract: The alliance of Apple, IBM and Motorola was formed with the vision of designing a microprocessor family able to span the scope of systems from microcontrollers to supercomputers with a common instruction set architecture and able to run common applications on all of the systems built using these processors The result was the PowerPC Architecture, a third-generation RISC architecture optimized for the diverse computing requirements of the future The Somerset Design Center was set up with the mission to jointly develop microprocessors based on the PowerPC Architecture

Two-out-of-two security data processing and arbitration apparatus and method

Abstract: The invention, which relates to the field of PowerPC architecture computer technology, provides a two-out-of-two security data processing and arbitration apparatus and method. The apparatus comprisesa first data processor, a second data processor and a data arbitration processor that use PowerPC architecture. The first data processor and the second data processor are respectively connected by a high-speed Serial RapidIO bus and a general-speed GPIO bus; and the data arbitration processor is respectively connected to the first data processor and the second data processor through two Ethernet switches. The first data processor, the second data processor, and the data arbitration processor are respectively connected to the Ethernet switch through an RGMII interface with a PHY mode. Therefore, synchronous processing, cross comparison and independent arbitration judgment of data in a rail transit signal system are realized; the reliability of the signal system is improved; the high operation safety of the rail transit is ensured; and technical problems of complicated structure, high power consumption, and poor reliability in the prior art are solved.

Asymmetric data processing device based on multi-core POWERPC processor

Abstract: The utility model discloses an asymmetric data processing device based on a multi-core POWERPC processor. The system is characterized in that the system comprises a multi-core POWERPC processor, an FPGA module, an Ethernet switching chip, a debugging connector connected with the Ethernet switching chip, a Rapidio switching chip and an interface connector connected with the Rapidio switching chip;one end of the FPGA module, one end of the Ethernet switching chip, one end of the debugging connector and one end of the Rapidio switching chip are connected with the multi-core POWERPC processor. And the other ends of the FPGA module and the Ethernet switching chip are respectively connected with the interface connector. The beneficial effects of the utility model are that the data processing device is high in real-time performance, strong in stability and strong in expansibility, provides higher performance and lower power consumption compared with a conventional data device, and avoids thedefects of a data processing device in the prior art.

Methods and apparatus for increased efficiency bus transactions

Abstract: Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

CPCI embedded navigation computer system and combined navigation algorithm

Abstract: The invention belongs to the field of system design, and discloses a CPCI embedded navigation computer system The CPCI embedded navigation computer system comprises a PowerPC embedded information processing board, an information acquisition pre-processing board, a data logging board and a power panel which are connected with one another through a CPCI bus, wherein the PowerPC embedded information processing board adopts a Vxworks system as an embedded operating system; the information acquisition pre-processing board is used for data caching during the information acquisition and information interaction processes of sensors, and CPCI interface between the information acquisition pre-processing board and the PowerPC embedded information processing board; the data logging board comprises a UART circuit, a memory array and a CPCI bridge interface circuit; FIFO control required by UART communication, PCI communication, data saving and data interaction can be realized by taking an ARM as the control core of the data logging board and adopting FPGA The computer system can meet the requirements of navigation and integrated navigation control, and is low in development cost, high in expandability, low in system energy consumption, and high in reliability and navigation precision