Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
Papers published on a yearly basis
Papers
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IBM1
TL;DR: This paper discusses several of the SOC design issues pertaining to dynamic voltage and frequency scalable systems, and how these issues were resolved in the IBM PowerPC 405LP processor and introduces DPM, a novel architecture for policy-guided dynamic power management.
Abstract: This paper discusses several of the SOC design issues pertaining to dynamic voltage and frequency scalable systems, and how these issues were resolved in the IBM PowerPC 405LP processor We also introduce DPM, a novel architecture for policy-guided dynamic power management We illustrate the utility of DPM by its ability to implement several classes of power management strategies and demonstrate practical results for a 405LP embedded system
58 citations
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01 Jan 2006TL;DR: This paper shows that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET, which is widely used in embedded systems, and some x86 models.
Abstract: Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrAƒÂ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.
58 citations
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IBM1
TL;DR: The PowerPC 620 RISC microprocessor is the first chip for the application server and technical workstation product line within the PowerPC family and utilizes a high performance microarchitecture with many advanced superscalar features to exploit instruction level parallelism.
Abstract: The PowerPC 620 RISC microprocessor is the first chip for the application server and technical workstation product line within the PowerPC family. It utilizes a high performance microarchitecture with many advanced superscalar features to exploit instruction level parallelism. It is the first 64-bit implementation of the PowerPC architecture supporting both 32- and 64-bit application software, and is compatible with the PowerPC 601, PowerPC 603, and PowerPC 604 microprocessors.
58 citations
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IBM1
TL;DR: Performance simulations show that the simplicity of a VLIW architecture allows a wide-issue processor to operate at high frequencies.
Abstract: Presented is an 8-issue tree-VLIW processor designed for efficient support of dynamic binary translation. This processor confronts two primary problems faced by VLIW architectures: binary compatibility and branch performance. Binary compatibility with existing architectures is achieved through dynamic binary translation which translates and schedules PowerPC instructions to take advantage of the available instruction level parallelism. Efficient branch performance is achieved through tree instructions that support multi-way path and branch selection within a single VLIW instruction. The processor architecture is described, along with design details of the branch unit, pipeline, register file and memory hierarchy for a 0.25 micron standard-cell design. Performance simulations show that the simplicity of a VLIW architecture allows a wide-issue processor to operate at high frequencies.
58 citations
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TL;DR: The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation, is reiterated and shortcomings in traditional Design for Manufacturability solutions are identified.
Abstract: The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous
patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing
layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed.
Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly
successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of
extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic
chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as
substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a
65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design
solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased
focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the
integrated process-design co-optimization, is introduced.
57 citations