PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture

Abstract: The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.

Partitioned System with XtratuM on PowerPC

Abstract: Nowadays, the diversity of embedded applications has been developed into a new stage with the availability of various new high-performance processors and low cost on-chip memory. As the result of these new advances in hardware, there is a great interest in enabling multiple applications to share a single processor and memory, which requires that each application must be in spatial and temporal isolation and protected from other applications in the same system. Meanwhile, this kind of isolation usually calls for the implementation at the level of safety/security-critical to guarantee the healthy running of the whole system. To realize the idea of multiple applications sharing single resource, from the point view of software, one approach is to implement the partitioned system. This concept originates from safety-critical areas such as MILS (Multiple Independent Levels of Security) architecture and ARINC 653 (Avionics Application Software Standard Interface) standard. It has been utilized a lot in real-time applications and safety-critical systems, etc. Aiming at the embedded applications, XtratuM is a real-time hypervisor originally built on x86 architecture. It is designed and implemented consulting the concept of partitioned system. As a hypervisor, XtratuM is located between the partitions and hardware. Partitions cannot directly access hardware but only via XtratuM. XtratuM enables partitions to execute simultaneously in spatial and tempal isolation without interfereing each other but sharing the same hardware. The main work in this thesis covers the implementation of XtratuM in PowerPC architecture. And some preliminary benchmarks have been carried out. This thesis is organized as follows: Chapter 1 shows the ideas and similar ideas about partitioned system, Chapter 2 describes XtratuM hypervisor, Chapter 3 introduces PowerPC, Chapter 4 expresses the main ideas for porting XtratuM to PowerPC, Chapter 5 states the implementation in detail, Chapter 6 shows the benchmark results and Chapter 7 concludes the work with future development.

A PowerPC based readout system for the silicon trackers of the H1-experiment

Abstract: The readout system of the H1 Central and Backward Silicon Tracker detectors is processing the data of about 120 000 analog readout channels. The strip data are digitized and processed by VMEbus Readout Processor Modules equipped with a local PCI bus and a 96 MHz PowerPC 604 processor. The processor performs a cluster search and reduces the raw data size by an average factor of 40. It also updates the pedestals and noise variances periodically. Events can be processed at up to 100 Hz, well matching the second level trigger rates.

Event Building in the ATLAS DAQ/EF Prototype “-1”

Abstract: In the framework of the ATLAS DAQ/EF prototype “-1” a stand-alone smallscale event building prototype has been developed in order to study the issues of switch-based parallel event building as needed for experiments at LHC. The event building prototype is designed in two layers: the technology-independent layer defines a high-level event building model, while the technology dependent layer uses commercially available interfaces and switches for a choice of three technologies: ATM, Fast Ethernet and Fibre Channel. The decoupling of the two layers is achieved by the means of a connection-oriented message passing library. The prototype has been implemented using PowerPC-based VME processors running a real-time UNIX operating system and works successfully with emulated input and output. The performance in terms of total throughput and protocol overhead for all three technologies has been measured.

The making of the PowerPC: introduction

Abstract: leadcrs join rogethrr to define a new srandard in coulpuring xchitecture. But that's rxa~-ll\\ what Apple, IBM, and Motorola harv done since ctm~hining fwces in the PoMerPC alliance. '\\I the Somcrsrt design facility in i\\ustin, Trxas, engineers from rach of the thrre companies design ~~owerP(: microprocessors , employing a formal \\:LSI drrigu Incthoclolo&y drawn from the hrst of IBhf's and Motornla'r dcvelopme~nr environmum \\Vith drsigns con,plcted on srhrdulc for the first IWO PowcrPC I,tmily mm-hrrs-the PowrPC 601 and P~werK: 603 rnicroproccssors-thr corn-puting inrhlel? can expect a steady stream of I'ow~rP(: microp~0ccwxs satisfying a broad range OS markrt rrquircnwnts to hr introduced iu the years to come. 'IX month'? issue of C~~~in~,l~,i,lll~~~n~ axers a wide range of topics surrounding the Powerf(: trrhnolo~~~, hcginning with a description by Moore and Stanphil1 of (he origins 01 the r~pplr-IRI\\I-~Motorola alliance itself al,d an owwirxv of the first genre-atirrn uf four distinct microprocessors drsignrd at Somerset. Thr PovxrPC arrhirrccs paid particular arrrnrinn to dctining PowrrPC Architecture details, making it llrxible and scalable, thus providing plenty of room for growth across a varied fan!+ of processors suit;rble 1(x a wide range of dlrcign-frum Iligll-prrlormance, multipro-cessing ~ysterns tu handheld computing devirrs. In addition, the drfin-ilion of the al-rhitrrrure ~nsores a guaranteed comn-lon software ellvironmrnt for opcrlrting systrm and applications softbare developers. Diefendorff describes the histon of I'ow~rP~~ Archirectuc evolution. De+ goals for thr PnwerP~~ 603 microprocessor were to delivrl Irigll-perfr)rmance RISC computing with powcr consumption IOM enough for portahlc laptop computing. Burger (il. a/. descrihc features of the PowrPC 60s implrmrnration: while Surssmi th and Paap f&us rh?ir attention to deails of the power management fwtures of the PowerPC 6O.Z microprocessor. Determining the impart ol~implernerr-tation choices on pcrformanre is an important elwwnt of modem processnr design. Poursepnnj dcscribrs thr merhodologv for p&or-nxmce modeling used hy Somzrsrt PowerPC designers. The weds of computer systems dcvclopers do not rnd with the processor silicon. High-quality compilers are ?qrrally important to the crration of high-performance systems. Shipnes and Phillip describe the modular appmach to the organiraion of Motorola's oprimied PowerP(; compilers. Incrrasingly important is thr Nell to begin soft-wre development and resting under software simulation hcfore systrm bar-duarc is axxilahlr. and Arderson provides an ovcl+err of Motorola's PowcrPC simulator family. The alliarrcc companirs, rogethcr and with their other partners, rnn-tinue to dcx~lop the other cl?ments nreded in a complete PowerPC computer s)-stem. A prcliminaly version of the PowerP(; Reference Platform Specification …