PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

IBM Research Report Efficient Instruction Scheduling with Precise Exceptions

Abstract: We describe the SPACE algorithm for translating from one architecture such as PowerPC intooperations for another architecture such as VLIW, while also supporting scheduling, register al-location, and other optimizations. Our SPACE algorithm supports precise exceptions, but in animprovement over our previous work, eliminates the need for most hardware register commit op-erations, which are used to place values in their original program location in the original programsequence. The elimination of commit operations frees issue slots for other computation, a featurethat is especially important for narrower machines. The SPACE algorithm is efficient, running in O(N2) time in the number of operations in the worst case, but in practice is closer to a two-pass O(N) algorithm.The fact that our approach provides precise exceptions with low overhead is useful to program-ming language designers as well — exception models in which an exception can occur at almostany instruction are not prohibitively expensive.

Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest

Abstract: This paper describes the hardware accelerated crypto sorter design submission for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. A speedup between 24 and 40 was achieved, when compared with the reference software only solution.

Implementation of CMNN Based Industrial Controller Using VxWorks RTOS Ported to MPC8260

Abstract: With the development of embedded Real Time Operating System (RTOS), dedicated controllers normally used to control single process loops are being replaced by shared controllers which are ported with RTOS running multiple control algorithms parallelly. This work demonstrates a Cerebral Model Neural Network (CMNN) based control algorithm being run as a real time application in MPC8260 (PowerPC) embedded processor with VxWorks RTOS. Process signals from the sensors are given to MPC8260 board through serial port and control signals transmitted to the actuator are displayed on a client system running Hyper-Terminal application.

Reconfigurable Systems and their Influence on Mobile and Multimedia Applications.

Abstract: With the advent of field programmable logic devices it became possible to design and implement digital systems without the need for the technological steps dealing with silicon. Tremendous progress in this area has made it possible to advance configurable microchips from programmable logic arrays - PLA (early 1970s) and further simple gate arrays, that appeared on the market in the mid-1980s, to platform field programmable gate arrays (FPGA) containing more than 10 million system gates and incorporating complex heterogeneous structures, such as PowerPC processors. Recent research results show that future programmable logic might achieve 100 billion devices per square centimeter, which permits to argue that cheap molecular-scale reconfiguration is likely to become the predominant digital technology in a decade hence. The impact of FPGAs on different development directions in computer science, electrical and computer engineering is growing continuously. Today, advanced research is being intensively performed in the areas of system-onchip and network-on-chip supported by the extensive use of computer-aided design (CAD) systems. Traditionally, FPGA-targeted CAD systems are based on schematic and hardware description language design flows involving model-specific tools and core generators. Recently, system level specification languages (such as Handel-C and SystemC) have been developed and are now frequently used. This clearly demonstrates that the domain of reconfigurable systems design is very dynamic and many-sided. The rapid evolution of FPGA technology and relevant CAD systems requires a large number of well-prepared engineers in these areas. Hence an ongoing review of the corresponding curricula is necessary to incorporate the recent advances. Consequently the impact of reconfigurable systems on contemporary engineering education is also growing continuously. This tutorial is intended to cover the majority of hot topics related to reconfigurable systems with a profound analysis and comparison of alternative approaches, such as hardware/software versus configware. It demonstrates advantages of reconfigurable systems in terms of technical characteristics and economic aspects and shows their significant influence on mobile computing and multimedia applications. The tutorial also includes a profound discussion of a novel methodology that has been used for teaching reconfigurable systems.

Measuring the effectiveness of various design validation approaches for PowerPC/sup TM/ microprocessor arrays

Abstract: Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for array design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, we propose a new way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. This technique provides a systematic way for the evaluation of the quality of various validation approaches. Experimental results using different validation approaches on recent PowerPC microprocessor arrays are reported.