PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Parallel Video Surveillance on the Multi-core Cell Broadband Engine

Abstract: The IBM Cell Broadband Engine (BE) is a multi-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in terms of memory latency, bandwidth and power computation. In this paper, we discuss the parallelization, implementation and performance of a video surveillance application on the IBM Cell BE. We report the Video surveillance application’s performance measured on a computer with one Cell processor and with varying numbers of synergic processor engines enabled. These results were compared to the results obtained on the Cell's single PPE with all 8 SPEs disabled. The results indicate that our video surveillance application performs approximately 16 times faster on the Cell BE than modern RISC processors by processing input data from five separate surveillance video streams in parallel.

Design tradeoffs and experience with Motorola PowerPC migration tools

Abstract: The Motorola PowerPC migration tools enable the conversion of assembly programs from other architectures to PowerPC. This paper describes the design approach and experience with the tool to translate x86 assembly programs to PowerPC. The key problems of handling 16-bit code, the effects of masking 16-bit operations into 32-bit registers and optimization of condition flags are discussed. The efficiency of translation and the effects of architectural constraints on design tradeoffs are analyzed.

Concepts for computer center power management

Abstract: Electrical power usage contributes significantly to the operational costs of large computer systems. At the Hypersonic Missile Technology Research and Operations Center (HMT-ROC) our system usage patterns provide a significant opportunity to reduce operating costs since there are a small number of dedicated users. The relatively predictable nature of our usage patterns allows for the scheduling of computational resource availability. We take advantage of this predictability to shut down systems during periods of low usage to reduce power consumption. With interconnected computer cluster systems, reducing the number of online nodes is more than a simple matter of throwing the power switch on a portion of the cluster. The paper discusses these issues and an approach for power reduction strategies for a computational system with a heterogeneous system mix that includes a large (1560-node) Apple Xserve PowerPC supercluster. In practice, the average load on computer systems may be much less than the peak load although the infrastructure supporting the operation of large computer systems in a computer or data center must still be designed with the peak loads in mind. Given that a significant portion of the time, systems loads can be less than full peak, an opportunity exists for cost savings if idle systems can be dynamically throttled back, slept, or shut off entirely. The paper describes two separate strategies that meet the requirements for both power conservation and system availability at HMT-ROC. The first approach, for legacy systems, is not much more than a brute force approach to power management which we call Time-Driven System Management (TDSM). The second approach, which we call Dynamic-Loading System Management (DLSM), is applicable to more current systems with ‘Wake-on-LAN’ capability and takes a more granular approach to the management of system resources. The paper details the rule sets that we have developed and implemented in the two approaches to system power management and discusses some results with these approaches. Copyright © 2009 John Wiley & Sons, Ltd.

A PowerPC platform full system simulation-from the MOOSE up

Abstract: Systems simulation is not new. Several instances of varying degrees have appeared over the last few years providing a diverse level of simulation capability. There are also a plethora of simulation kernels and simulation environments available today. Each of these has strengths and weaknesses usually centered around the specific environment to which the simulation is targeted. During the mid-1990s there were no other publicly available simulations that provided what we considered to be a complete functional system simulation environment. This paper presents the PowerSim simulation environment and the MOOSE simulation kernel. PowerSim is a full system simulation of a PowerPC computer platform capable of running unmodified complex operating systems and applications. MOOSE (Motorola Object-Oriented Simulation Environment) is simulation kernel capable of running distributed object-oriented simulations in an efficient, synchronized manner. In this simulation environment, it is possible to analyze an almost unlimited set of applications and systems software.

General nuclear core plate based on powerPC configures central processing unit

Abstract: The utility model discloses a general nuclear core plate based on powerPC configures central processing unit, including central processing unit, field programmable gate array, communication unit, memory cell, temperature sensor and real -time clock module, wherein, does field programmable gate array pass through PCI E interface, SRIO interface, LBC interface, GPIO interface and IRQ interface are connected with central processing unit, communication unit includes general asynchronous receiving and dispatching transmitter and ethernet module, and general asynchronous receiving and dispatching transmitter passes through the RS232 interface and is connected with central processing unit to too the wire mould piece passes through II interfaces of RGM and is connected with central processing unit, memory cell includes SD card, norFlash, nandFlash, USB controller and DDR3, and nandFlash passes through eLBC interface connection central processing unit, and DDR3 passes through the memory controller and connects central processing unit. The utility model provides a general nuclear core plate, the integrated level is high, small, the peripheral hardware interface is abundant, being suitable for integratedly to user's target integrated circuit board in, shortens product development time of designer.