PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Off-chip delta-I noise modeling and measurement methodology

Abstract: This paper describes an electrical modeling and measurement methodology for high-speed simultaneous switching noise generated by off-chip drivers. It details the study of package parasitic effects on the component electrical performance in a functional system environment. Critical design parameter curves are generated and correlated with hardware measurements under an actual system environment. A novel measurement technique is also described which facilitates the understanding of the modeling results for the integrated system. Actual hardware measurements of state-of-the-art PowerPC/sup TM/ microprocessor designs are used to justify the modeling technique.

Multi-core and optical processor related applications research at oak ridge national laboratory

Abstract: High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed bymore » an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

Automatic Link Editor Generation for Embedded CPU Cores

Abstract: SoC design space exploration requires code generation for several CPU core alternatives. However, an embedded software code generation toolkit cannot be developed from scratch for every target CPU under exploration. Nor can it always be reused from standard packages, especially when the CPU core is an ASIP. That?s why automatically retargetable tools are required. This paper describes a retargetable technique for link editor automatic generation from a formal description of the target CPU core. The implementation of the technique relies on the well-known GNU binutils package. To make it retargetable, the key is to reuse the architecture-independent libraries and automatically generate the architecture-dependent ones. The technique?s correctness and robustness were verified for three target CPUs (MIPS, SPARC and PowerPC) running programs from the benchmark MiBench. For experimental validation, we have successfully compared the executable files produced by the generated tools to those produced by conventional tools from the GNU binutils package.

Automatically Generating Back Ends for a Portable Assembly Language Using Declarative Machine Descriptions

Abstract: We show how to generate the back end of an optimizing compiler from a formal description of the syntax and semantics of machine instructions. Our generated back ends for x86, ARM, and PowerPC perform as well as their hand-written counterparts. Automatic generation is enabled by two new ideas: a model of machine-level computation that reduces back-end generation to the problem of finding implementations of about a hundred simple, machine-level operations; and an algorithm that finds these implementations by c ombining machine instructions.

U-Boot Booting Analyses and Porting on PowerPC Platform

Abstract: The bootloader is the first piece of program after the system is powered on, which is mainly intended to initialize hardware devices, preparing for loading OS kernel.U-Boot is a bootloader program of popular and open source code.According to the hard-ware platform for high-speed data transmission based on MPC8349E processor, the paper analyzed U-Boot's booting sequence, and then introduced porting process and ways on the system design of PowerPC platform.