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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
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Patent
30 Apr 2014
TL;DR: In this paper, the utility model discloses a PowerPC signal data switching board which comprises a back board bus, an FPGA, a first SRIOSwitch and a second SRSwitch.
Abstract: The utility model discloses a PowerPC signal data switching board which comprises a back board bus. The back board bus is connected with an FPGA, a first SRIOSWITCH and a second SRIOSWITCH. The first SRIOSWITCH and the second SRIOSWITCH are connected in series. The FPGA and the first SRIOSWITCH are connected with a PPC. The PPC is connected with a PHY chip, a Uart, a DDR2SARAM and a NORFLASH memory. The PowerPC signal data switching board provided by the utility model has the advantages of fast data switching speed, low power consumption and high stability and reliability.

1 citations

Posted Content
TL;DR: In this article, the authors describe the interface and integration issues driven by project, cooling system and vacuum system requirements and hardware selections for the Spallation Neutron Source (SNS) linac.
Abstract: External contractors are developing the local cooling and vacuum control systems for the Spallation Neutron Source (SNS) linac. Soon these systems will be integrated into the facility-wide controls system. Allen-Bradley Logix5000 series programmable controllers, populated with appropriate input/output modules, were selected as the local controllers. These controllers will be interfaced to the facility-wide control system via VME systems with PowerPC processors running the Wind River VxWorks operating system and Experimental Physics and Industrial Control System (EPICS) front-end controller software. This paper describes the interface and integration issues driven by project, cooling system and vacuum system requirements and hardware selections.

1 citations

Proceedings ArticleDOI
A. Kumar1, B. Waldecker
24 Jun 1997
TL;DR: The methodology used and the results obtained in studying design trade-offs for the PowerPC family of processors and system designs using these processors show that system performance is sensitive to the access distance of L2 and L3 caches for many cache sizes and workloads.
Abstract: Presents the methodology used and the results obtained in studying design trade-offs for the PowerPC family of processors and system designs using these processors. Specifically, the effects of various cache hierarchies and multiprocessor designs on system performance are examined. Issues dealt with include the performance speedup for different multiprocessor configurations and memory subsystem designs when executing various workloads. Four generic types of workloads were studied. They are defined such that most actual applications should fit into one of the four categories. Results obtained show that system performance is sensitive to the access distance of L2 and L3 caches for many cache sizes and workloads. Required versus available bus bandwidth was examined and found to not be a problem for the systems and workloads under consideration.

1 citations

Proceedings ArticleDOI
01 Dec 2009
TL;DR: A framework is presented which enables development of parallel programs across application-specific reconfigurable hardware using simple hardware interface abstractions and standard MPI application structure.
Abstract: With falling costs and successful demonstrations of performance, FPGAs have become a prime candidate for use in high performance computing. However, the use of FPGA technology in clustered environments has largely been limited to commercial and/or proprietary designs that require developers to learn new programming models and software tools. In this paper, a framework is presented which enables development of parallel programs across application-specific reconfigurable hardware using simple hardware interface abstractions and standard MPI application structure. This approach leverages commodity technologies including embedded Linux running on hardwired PowerPC processors to manage communication such that each hardware acceleration unit can function as a fully MPI-2 compatible node. The implied hardware/software design and programming model are discussed and an application case study is presented to demonstrate functionality and elucidate platform benefits through performance analysis.

1 citations

Journal ArticleDOI
Qiang Yu1, Zhang Gang1, Peng Fei Yu1, Hui Huang1, Wei Chen1 
TL;DR: For software function verification and performance testing, a test platform was built during the development of large-capacity EPON OLT equipment based on distributed system using modified TCP/UDP to establish RPC data exchange path between nodes.
Abstract: For software function verification and performance testing, a test platform was built during the development of large-capacity EPON OLT equipment. The platform was based on distributed system,which using modified TCP/UDP to establish RPC data exchange path between nodes. With Linux as unified operating system, software work in both embedded PowerPC and x86-based PC virtual machines without modification. At last, a group of stress test was executed on the platform and the result was discussed.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823