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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


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Proceedings ArticleDOI
28 May 2013
TL;DR: This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder that supports QCIF and CIF video formats with temporal and spatial scalability.
Abstract: This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high‐level synthesis methodology to RTL microarchitecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The final implementation is chosen among the implementations that meet the timing constraints. The DF is capable to run at 100 MHz, and macroblocks are processed in 6,500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. The proposed architecture for the complete H.264/SVC decoder is composed of an OMAP 3530 SOC (ARM Cortex‐A8 GPP + DSP) and the FPGA Virtex‐5 acting as a coprocessor for DF implementation. The DF is connected to the OMAP SOC using the GPMC interface. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the frame generation and visualization in a TFT screen. The FPGA implements both the DF core and a GPMC slave core. Both cores are connected to the PowerPC440 embedded processor using LocalLink interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device.
01 Jan 1995
TL;DR: In this paper, transient energy management strategies are introduced via examining chip-on-substrate geometry and evaluating transient thermal management case study on PowerPC based model notebook computer, where cascaded frequency reduction, periodic heating and workload shifting techniques for dynamically controlling chip junction temperature are discussed.
Abstract: Transient energy management strategies are introduced via examining chip-on-substrate geometry and evaluating transient thermal management case study on PowerPC based model notebook computer. Cascaded frequency reduction, periodic heating and workload shifting techniques for dynamically controlling chip junction temperature are discussed. Model notebook computer case study indicates that it is possible to improve notebook computer performance dramatically by using high end processor and transient thermal storage cooling techniques.
Proceedings ArticleDOI
17 Jan 2006
TL;DR: The inclusion of the calibration pins has induced an uncommon structure where two balls in the package are sharing a pad on the die, which has created some test challenges.
Abstract: VertiCal is a calibration system for eSys, a family of 32-bit automotive microcontrollers based on the PowerPC architecture. To utilize the calibration system, a common scale package among the derivatives is required and a table of universal pin locations including the calibration pins is properly defined. However, the inclusion of the calibration pins has induced an uncommon structure where two balls in the package are sharing a pad on the die. This structure has created some test challenges. This paper discusses in detail the problem, followed by approaches in analysis and experimental results.
01 Jan 2001
TL;DR: The views and conclusions contained herein are those of the authors and should not interpreted as necessarily representing the official policies or endorsement, either expressed or implied, of the Defense Advanced Research Projects Agency, Air Force Research Laboratory, or the U.S. Government.
Abstract: The growing gap in performance between processor and memory speeds has created a problem for data-intensive applications. A recent approach for solving this problem is to use processor-in-memory (PIM) technology. PIM technology integrates a processor on a DRAM memory chip, which increases bandwidth between the processor and memory. In this paper, we discuss two PIM-based multiprocessor systems, the System Level Intelligent Intensive Computing (SLIIC) Quick Look (QL) board and a hypothetical V-IRAM multiprocessor board. The former system includes eight COTS PIM chips that are connected by a flexible FPGAbased interconnect network. The V-IRAM board modeled contains four Berkeley V-IRAM PIM processors (currently under development) that are connected using FPGAs. The performance of several data intensive applications on the SLIIC QL board is measured. The performance of the applications on the V-IRAM board is modeled at the clock cycle level. The performances of these boards are compared with a PowerPC-based multicomputer and a Pentium system.
01 Jan 2010
TL;DR: In this article, the authors investigated the performance of many-core ar-chitectures for the acceleration of wavefront applications and focused on graphics processing units (GPUs) in particular.
Abstract: We are currently investigating the viability of many-core ar-chitectures for the acceleration of wavefront applications andthis report focuses on graphics processing units (GPUs) inparticular. To this end, we have implemented NASA’s LUbenchmark [1] { a real world production-grade application {on GPUs employing NVIDIA’s Compute Uni ed Device Archi-tecture (CUDA) [2].This GPU implementation of the benchmark has been used toinvestigate the performance of a selection of GPUs, rangingfrom workstation-grade commodity GPUs to the HPC \Tesla"and \Fermi" GPUs. We have also compared the performanceof the GPU solution at scale to that of traditional high perfor-mance computing (HPC) clusters based on a range of multi-core CPUs from a number of major vendors, including Intel(Nehalem), AMD (Opteron) and IBM (PowerPC).In previous work we have developed a predictive \plug-and-play" performance model of this class of application runningon such clusters, in which CPUs communicate via the MessagePassing Interface (MPI) [3, 4]. By extending this model toalso capture the performance behaviour of GPUs, we are ableto: (1) comment on the e ects that architectural changeswill have on the performance of single-GPU solutions, and(2) make projections regarding the performance of multi-GPUsolutions at larger scale.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823