Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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01 Jan 2002
TL;DR: The Mouton Interactive Introduction to Phonetics and Phonology: An Interactive Introduction (2000; Contains bonus program Introduction to Voice Onset Time, 1996)
Abstract: Title The Mouton Interactive Introduction to Phonetics and Phonology (2000) Phonetics: An Interactive Introduction (2000; Contains bonus program Introduction to Voice Onset Time, 1996) Author Jurgen Handke Nicholas Reid, with contributions from Helen Fraser Platform Windows (9x/ME/NT 4.0/2000) and Macintosh (MacOS 8.1 or higher) Windows (95/98/NT4) and Macintosh (MacOS 7.5.1 or later) Minimum hardware requirements PC: Pentium, 32 MB RAM, 30 MB hard disk space, SVGA graphics board, CD-ROM drive and sound card. Mac: PowerPC 120 MHz or higher, 32 MB RAM, 30 MB hard disk space, screen resolution 800x600, color monitor with thousands of colors or higher, CD-ROM drive, sound card. PC: Pentium processor or equivalent, 2x speed CD-ROM, 12 MB RAM (free), 800x600 8-bit color display. Mac: 68040 or faster processor, 2x speed CD-ROM, 12 MB RAM (free), 800x600 8-bit color display.
01 Jan 2009
TL;DR: An unied abstraction layer has been implemented to en-capsulate the GPGPU scheme and the motivation is to allow different device layers to be implemented around the various GPUs and data parallel APIs such as OpenCLor DirectX compute shaders.
Abstract: Thefundamentalgoalsofthecoreenginearespeed,per-formance and resource usage. Recently we have focu-sed on portability and platform support. Developing ahighly scalable single code base which can make use ofwiderangeofhardwareisasignicantchallenge,inpar-ticular the engine should be able to scale up and downwith the target hardware. The recent efforts to realizethis aim are as follows: TosupportGraphicsProcessingUnits(GPUs)andparallel processors from multiple vendors. Alayered approach has been added to allow dif-ferent device specic Application ProgrammingInterfaces (APIs) to be evaluated more easily. For the PowerPC and other big endian processorsthe byte ordering is automatically handled inter-nally to allow binary compatibility with the stan-dard x86 byte ordered models. The decoder has been compiled and tested onUnix, Windows and MacOS platforms and onx86, AMD64, PowerPC and ARM (via an emu-lator) processors.2.1 Layered Acoustic ScoringA unied abstraction layer has been implemented to en-capsulate the GPGPU scheme we proposed in [4]. Un-derneath this layer various device layers are used to per-form the actual computation. The motivation is to allowfor different device layers to be implemented around thevarious GPUs and data parallel APIs such as OpenCLor DirectX compute shaders. Device layers are not justrestricted to GPUs, alternatively they could be the Sy-nergistic Processing Units (SPUs) on the Cell processor,a conventional multicore processor or a totally differentclassofadevicesuchasaFieldProgrammableGateAr-ray (FPGA).The abstraction layer provides the high level inter-faces needed by the decoder to create the matrices ofacoustic parameters and launch the transfers or compu-tations. A Synchronization barrier is also available toallow the acoustic computations to be performed in anasynchronous fashion. In this overlapped mode the up-coming acoustic scores are computed whilst the searchalgorithm operates on the current window of acousticscores.2.2 High-level APIPreviously there were two levels at which to interactwith the T
18 Nov 2008
TL;DR: The article shows a schedule synthesis techniques minimising makespan or sum of completion times criterion and presents a synthesis methodology considering a fraction of resource capacity, called resource budget and maximization of processor utilization for tasks with bounded period.
Abstract: Some digital signal processing applications can be executed faster by moving parts of application implementation into hardware. Platforms, like Xilinx Virtex-4 4VFX12, allow a user to run software in embedded processor and offload computations to the set of hardware modules. The article deals with optimal schedule synthesis techniques for tasks executed on such platform using priced timed automata and UPPAAL CORA tool. It shows a schedule synthesis techniques minimising makespan or sum of completion times criterion. Moreover, it presents a synthesis methodology considering a fraction of resource capacity, called resource budget and maximization of processor utilization for tasks with bounded period. Case studies and FPGA experiments are finally presented.
14 Jul 1997
TL;DR: The Harbinger system is a PowerPC-based SCI multiprocessor system, the non-uniform Memory Access (NUMA) paradigm results from a distributed shared memory system with several levels in the memory hierarchy.
Abstract: The Harbinger system is a PowerPC-based SCI multiprocessor system. In this multiprocessor, the non-uniform Memory Access (NUMA) paradigm results from a distributed shared memory system with several levels in the memory hierarchy. The development of the Harbinger system continues through a series of stages of both hardware and software design. The hardware development begins with a standard development system design and progresses from custom hardware with, initially, uniprocessor logic to, finally, multiprocessor shared memory logic. The software design progresses, first, from porting a commercial operating system to the standard development system to, later, our custom hardware SCI based shared-memory system.
01 Jan 2000
TL;DR: The Binary-translation Optimized Architecture (BOA), an implementation of the IBM PowerPC family, combines binary transla-tion with dynamic optimization to simplify the hardware by bridging asemantic gap between the PowerPC RISC instruction set and even sim-pler hardware primitives.
Abstract: igh-frequency design and instruction-levelparallelism (ILP) are two keys to high-performance microprocessor implementa-tions. The Binary-translation OptimizedArchitecture (BOA), an implementation ofthe IBM PowerPC family, combines binary transla-tion with dynamic optimization. We use these tech-niques to simplify the hardware by bridging asemantic gap between the PowerPC RISC (reducedinstruction set computer) instruction set and even sim-pler hardware primitives.Processors like the Pentium Pro and Power4 havetried to achieve high frequency and ILP by imple-menting a cracking scheme in hardware: An instruc-tion decoder in the pipeline generates multiplemicro-operations that can then be scheduled out oforder. BOA relies on an alternative software approachto decompose complex operations and to generateschedules. Software allows more elaborate scheduling and opti-mization than hardware. Thus, you can use softwareto eliminate complex control hardware so that aprocessor implementation based on binary translationcan achieve maximum performance by enabling high-frequency processors while still exploiting availableparallelism in the code.Our work on BOA was inspired by earlier binarytranslation work such as FX!32