PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

스마트무인기 비행운용프로그램 개발

Abstract: The operational flight program(OFP) which has the functions of I/O processing with avionics , flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

VHDL token-based performance modeling for 2D and 3D infrared search and track processing

Abstract: This study develops and evaluates a new VHDL-based performance modeling capability for multiprocessor systems. The framework for this methodology involved modeling the following system aspects: processor characterization, task modeling. network characterization, and data set size. Initially, all aspects are specified at an abstract) level, and eventually become specified at a detailed level through the process of verification and refinement of design assumptions. Processor characterization involves modeling the processor's speed, instruction set, and memory hierarchy. Task modeling is concerned with the execution time and instruction mix of software tasks within the system. Network characterization models bus protocols, topology, and bandwidths. Data set size refers to how much data is represented by the tokens used in the models. In this study, we applied and evaluated this methodology using both two-dimensional (2D) and three-dimensional (3D) infrared search and track (IRST) algorithms. Two different candidate processors were investigated: IBM PowerPC 604 and Texas Instruments TMS320C80. For the 2D IRST algorithm, the abstract and detailed performance modeling results were obtained for both processors using partitioned data and pipelined algorithmic approaches. For the 3D IRST algorithm, performance models for pipelined and parallelized implementations on the PowerPC were developed. These models examined the feasibility of the implementations, the potential risk areas, and laid the groundwork for detailed performance modeling.

Development of BGA Solution for the IBM PowerPC 970 Module in Apple's Power Mac G5 Presented at ECTC 2004

Abstract: Apple's Power Mac G5 systems use either one or two IBM PowerPC 970 chips. Initial systems built with the PowerPC 970 64-bit processor run at speeds up to 2.0 GHz. These chips are packaged on IBM ceramic BGA (Ball Grid Array) modules. The high performance modules dissipate high power, which presents new packaging challenges. One of these challenges has been addressed successfully by improving the thermo-mechanical integrity of the solder interconnections between the chip carrier module and the organic processor board. The PowerPC 970 chip dissipates high power in a small area and is aggressively cooled using a state-of-the art heatsink design. A high clamping load is applied at the chipto-heatsink interface to enable the highest level of heatsink performance and to protect the CPU assembly from potential thermal degradation resulting from shock and vibration. The applied compressive load on the module led to additional focus on ensuring the reliability of the Ball Grid Array (BGA) connections between the PowerPC 970 module and the G5 system processor card. The G5 system uses an aggressive power management control system to reduce the chip power when the demands on the processor are low. This results in additional cumulative strain on the interconnection materials, particularly for those with significantly different Coefficients of Thermal Expansion (CTEs). The PowerPC 970 module is connected to a G5 system processor card with a significantly higher CTE. The design team was challenged to eliminate any risk of cyclic fatigue of the BGA at that interface. The BGA reliability evaluation effort focused on characterizing the impact of the applied compressive load on the solder ball grid array (BGA) connections between the PowerPC 970 module and G5 system processor card, improving the mechanical integrity of the CBGA array, and mitigating long term reliability risk due to creep and cyclic fatigue.

Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems

Abstract: Timing analysis of embedded systems is an operation performed when there are tasks that have to execute with a well precise deadline, and need to be scheduled, such as those on real-time systems. The diffusion of embedded systems to different kind of application areas is driving platforms toward heterogeneous multi-core architectures, that require a timing analysis done by using measurement based techniques. Measurements collection, when done via an instrumentation of the application, can cause an overhead in the execution time, footprint and necessary space to store data, that can affect the behaviour of the system. In such a scenario, this work proposes a framework that allows a user to quickly perform instrumentation choices, by using a concept named Time Band, and to have a direct feedback about the impact of its choices on some performance parameters. Time Band is then applied to Rapitime, a diffused timing analysis tool, and first tests have been done on IA-32 and PowerPC architectures, showing the advantages of different techniques the can be applied to realize the framework.

Automated test model generation from switch level custom circuits

Abstract: Custom VLSI design at the switch level is commonly needed when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models for custom logic are created manually from the switch level models - a tedious, error-prone process requiring experienced DFT engineers. This paper presents an automated flow for creating gate level test models from circuits at the switch level. Besides providing comparable test quality, the test model created by automated flow maintains structural similarity to the original switch-level circuit which facilitates failure analysis greatly. The automated flow has been in use for the past several years within Motorola for the high performance processor family implementing the PowerPC instruction set architecture. We present experimental results on MPC7455.