PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

60X bus bridging system and method based on FPGA and medium

Abstract: The invention provides an FPGA (Field Programmable Gate Array)-based 60X bus bridging system, an FPGA-based 60X bus bridging method and a medium. The FPGA-based 60X bus bridging system comprises a main bridge control module which carries out decoding processing on the 60X bus of the PowerPC processor so as to acquire address decodes and output control information and the address decodes; And a DDR2 control module which is used for caching the DDR communication data from the 60X bus according to the received control information and controlling the external DDR2 memory logic. The system has an independent 60X bus response time sequence technology, is not influenced by an external module, and can ensure the stability of the processor, and each bus interface has a plurality of caches which aremutually independent at the same time, so that the response time of the processor is shortened, and the bus access rate is improved. According to the invention, the PowerPC processor is connected with the FPGA chip, and the 60X bus is converted into each peripheral chip interface by using the FPGA, so that an original 60X special-purpose bridge switching chip is replaced; Performance is higher, connection is flexible and convenient, and expansion is easy.

Design and implementation of multi-channel CAN communication interface based on embedded linux

Abstract: According to the communication and control requirement of multi-channel Control Area Network(CAN) bus by the HLA simulation platform, this paper described a embedded PowerPC system based method of design and implementation of multi-channel CAN communication platform. The corresponding Linux multi-channel CAN device driver has also been developed. This flexible system can connect to different number of CAN daughter boards. It can work stable with low CPU usage under the condition of high data rate on multi channels.

Efficient in-system RTL verification and debugging using FPGAs (abstract only)

Abstract: FPGAs have become indispensible in processor design, bring-up and debug. Traditionally FPGAs have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, as the complexity of processors grows, another aspect of processor design, RTL verification, has become a prime target for acceleration using FPGAs. Software-only RTL simulation and verification tools are no longer sufficient for many verification tasks as they often incur long execution time penalties. Software simulation time for a basic Linux kernel bring-up on a BlueGene/Q [1] processor, with 16 user PowerPC A2 cores, for example, could easily exceed several years.An important feature of RTL verification acceleration using FPGAs is its fast debugging capabilities. The ability to quickly and accurately pinpoint the location of an anomaly in an RTL source is highly desirable. This paper proposes efficient in-system debugging techniques on FPGAs for RTL verification. We show how a network of over 45 Virtex 5 LX330 FPGAs can be efficiently used to read out state information of the BlueGene/Q processor. We also demonstrate how the new in-system debugging technique is 250x faster than comparable methods.

Offline test method and device based on PowerPC multi-core processor

Abstract: An embodiment of the invention provides an offline test method and device based on a PowerPC multi-core processor. The method includes determining a target program to be tested when the PowerPC multi-core processor is in the multi-core multi-process running state and needs to be tested off line; loading a test task for the target program; extracting a test case from the target program; executing the test case using a simulation interface; ending and deleting the test task when the test case is executed. The method solves the problem in the prior art that software compiling loading consumes long time and the multi-core multi-process timing sequence cannot be simulated or tested due to the fact that repeated compiling, linking and loading of the program must be performed when the test case not passed is executed singly. The working efficiency of an embedded program system is improved in the multi-core multi-process architecture mode, and the completeness and the reliability of the test are also ensured.

PEFP monitoring system through an Analog Input to Ethernet Converter

Abstract: Proton Engineering Frontier Project (PEFP) has above 40 magnet power supplies for the 20 MeV proton linac. Because some power supplies have analog interfaces, we chose ATEC (Analog Input To Ethernet Converter) to monitor their output currents and voltage by supporting the protocol conversion function. Software components of the Experimental Physics and Industrial Control System (EPICS) have been ported to a VME single board computer based on a Power PC microprocessor (MPC7410). This paper presents the software component and processing of analog input values between EPICS on the PowerPC based board and ATEC operating as Server Mode.