PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

PSO: Shared Symbol Space for Multicomputer Architectures

Abstract: The Public Shared Objects run-time system (PSO) is an attempt to offer advantages of Virtual Shared Memory for distributed memory parallel computers without a significant loss of performance. Shared data structures are distributed via the network to processing nodes and may exceed the capacity of local memory. Provided access objects hide access latency. The process of parallel program design is shortened and facilitated significantly. PSO is a portable software solution extending the C++ programming language. It has been implemented for the PARIX software environment and is available for parallel com puters based on Transputers or PowerPC processors. Reference applications in the fields of device simulation and image processing offer high efficiency for up to 128 processors.

Research and Design of Vehicle Simulation Subsystem of Testing Platform for CBTC System Based on Linux PowerPC

Abstract: According to the operational principle and functional requirements of testing platform for CBTC system, this paper focuses on the research and design of vehicle simulation subsystem of this testing platform. First of all, through the analysis of the functions of the CBTC testing platform, the design scheme of the vehicle simulation subsystem is completed. Then, under the PowerPC hardware platform and software platform based on embedded Linux operating system, the hardware design of the unit adapter and the development process of BSP driver between the vehicle subsystem and the CBTC testing platform are introduced in detail. Finally, the vehicle simulation subsystem is realized by establishing the vehicle dynamic model and developing the master computer. The subsystem is connected to the CBTC testing platform, and multiple actual line data and different EMU data are used for testing, which verifies the feasibility and versatility of the system.

Nesting exception processing circuit and method for embedded PowerPC (performance optimization with enhanced RISC (reduced instruction set computer)-performance computing) processor

Abstract: The invention provides a nesting exception processing circuit for an embedded PowerPC processor. The circuit comprises a processor core, an internal memory access circuit, a detecting circuit for detecting internal exception of the processor, a pause control circuit for enabling the processor to enter a stopped state, and a set of reset control circuit for resetting the processor. The nesting exception processing circuit for the embedded PowerPC processor is characterized by also comprising a master control switch circuit, a read-write memory control bit, a read-write memory flag bit containing information that whether nesting exception takes place, a group of memory flag segments containing the latest exception type numbers of nesting exception events, and a read-write memory control bit for controlling an nesting exception processing method. The nesting exception processing circuit and method for an embedded PowerPC processor can effectively prevent the PowerPC processor from entering a crash or chaos state due to nesting exception.

Combining generic programming with vector processing for machine vision

Abstract: This thesis addresses the integration of generic programming with vector processing for machine vision. While generic libraries have been shown to provide near optimal performance without sacrificing flexibility and adaptability, current generic libraries do not utilise the vector processing unit (VPU), nor can they be vectorised directly. Generic vectorised libraries require a mechanism for expressing vectorised algorithms independently of the VPU. This is a problem since different VPUs can have different instructions and different limitations; programs written to use one vector technology are not portable to other vector technologies. Lastly, most existing machine-vision libraries do not provide image capture from sequence grabbers; the programmer has to use another library to capture images, and to supply additional code to enable the two libraries to work together. To allow vectorised, machine-vision algorithms to be portable across different vector technologies, this thesis proposes the use of an abstract VPU. The abstract VPU represents a set of real VPUs with a virtual VPU that has an idealised instruction set and constraints common to the real VPUs being represented. An abstract VPU, named Virtual Vector Machine (VVM), was developed to support generic programming. Different methods of implementing VVM were evaluated against hand-coded AltiVec (a vector technology found in PowerPC G4 and G5 processors) and scalar programs. The implementation chosen has no significant overheads when processing VVM vectors with a single AltiVec vector or a single scalar when compiled using Apple GCC 3.1 20021003. VVM vectors with a single AltiVec vector or scalar cover all byte AltiVec vectors in AltiVec mode and all types in scalar mode. When processing VVM vectors that use more than one AltiVec vector, the VVM implementation chosen is within 24% slower than a hand-coded program. Vectorised algorithms are difficult to implement, because they handle VPU-specific issues such as memory alignments, edges and prefetching. Thus, to reduce the number of algorithms required, a categorisation of image processing operations based on input-tooutput correlation is proposed. This categorisation maps easily to generic programming and provides implementation hints. The categorisation scheme separates image processing operations into three categories, which this thesis refers to as quantitative, transformative and convolutive operations. Quantitative operations require one input element to produce zero or more output elements. Transformative operations require one input el-

Multithreading Issues on Contemporary PowerPC Microprocessors

Abstract: Contemporary high performance microprocessors are moving beyond faster clocks and wider busses to meet the growing demands for computational power. Techniques such as multiple threads of execution and heterogeneous processing cores are becoming more mainstream bringing with them interesting challenges for operating system and application developers alike. Fast synchronisation algorithms and lockless data structures are finding increasing relevance when applied to applications and operating systems running on these microprocessors. In this Literature Review we seek to gain an understanding of the state of the art for these types of algorithms, contemporary microprocessors and the benchmarks used to quantify their performance. Armed with this we intend to develop a plan of research so that we might contribute to the body of knowledge through work in COMP6702 in Semester 2, 2006.