PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload

Abstract: This paper describes the key circuit features of the 32 KB data cache memory embedded in the first AltiVec/sup TM/ enhanced PowerPC/sup TM/ microprocessor. The memory array implements a castout/reload scheme that allows both a read and a write operation within a single machine cycle which greatly increases cache bandwidth. A newly implemented vector alignment multiplexer supports the additional vector instructions. The design incorporates self-resetting and dynamic circuit techniques to achieve a cycle time of less than 2.0 ns fabricated in a 1.8-volt, 0.2 /spl mu/m, 6-layer copper CMOS process.

Wool--A C library for OSE PowerPC Multi-Core system

Abstract: With the requirement of high property processor rapidly increasing, ordinary single-core processors can hardly deal with the task it faces due to the limitation of frequency, power consumption, heat dissipation and etc. Under this circumstance multi-core processor technology turns out to be a reasonable solution for this problem. While multi-core processors will improve the performance like clock frequency, parallel threads and etc, a certain research illustrate that the improvement of the performance is not linear with the number of cores. This is because the overhead of scheduler, unbalanced load and the architecture of the multi-core processors. When operating system gives good model like SMP, AMP and industry like X86 and PowerPC design kind of architecture for multi-core, author’s direction naturally focus on a light overhead scheduler which is a C language scheduler “Wool” researched in this paper originally designed by Mr. Karl-Filip Faxen in SICS. Wool is a library providing lightweight tasks on top of pthreads. [4] In order to understand the principal and structure of “Wool”, author does several pre-study about multi-core schedule and decides the platform and operating system to design some tests. The first part of this master thesis report give an overview of modern technology of multi-core architecture, parallel programming, task parallelism strategy and etc. The second part specified the “Wool” scheduler. PowerPC e500 core and Enea OSE operating system for the test design and use case. The last part conclude the results of the tests and point out the probably direction for future research.

Optimizing large scale CUDA applications using input data specific optimizations

Abstract: CUDA applications and general-purpose GPU (GPGPU) programs are widely used nowadays for solving computationally intensive tasks. There is a substantial effort in the form of tools, papers, books and features that are targeted at GPGPU APIs such as CUDA and OpenCL. The GPU architecture, being substantially different from the traditional CPU ones (x86, PowerPC, ARM) requires a different approach and introduces a different set of challenges. Apart from the traditional and well examined GPGPU problems - such as memory access patterns, parallel designs and occupancy, there is yet another really important, but not well studied setback - from one point onward, the bigger the CUDA application gets (in terms of lines of code) the slower it becomes, mostly due to register spilling. Register spilling is more or less a problem for most of the available architectures today, but it can easily become a massive bottleneck on the GPU due to its nature. We are going to examine in detail why this happens, what are the common ways to solve it, and we are going to propose one simple, presently undocumented approach that may be used to alleviate the issue in some situations. For the purpose of this paper we will focus on the NVidia Fermi Architecture

Implementing the Matrix Exponential Function on Embedded Processors

Abstract: : In this paper we describe and benchmark an implementation of the matrix exponential function. The implementation is based on the standard technique of scaling and squaring from the literature. The major kernels in this technique are matrix multiplication and Gaussian elimination. In the matrix multiply kernel, the implementation makes use of SIMD vector extensions present on the PowerPC G4 (Altivec) and the Intel Xeon (SSE-2). Although the use of the matrix exponential expands the operation count of the extended Kalman filter substantially, benchmarks of the implementation show that the workload is well within the capabilities of modern processors.

Highly integrated modular avionics from platform to payload for micro-satellites

Abstract: Low-cost, intelligence and short development cycle has become its trend of small satellites. A hybrid on-board avionics topology based on CAN bus and router was proposed. The telemetry was collected by On-Board Computer (OBC) via CAN bus, while the router integrated RS422, LVDS, Ethernet, Camera Link and TLK2711 interfaces, which support data rate varying from 1Mbps to 10Gbps and usually used by payloads, so it makes regular payloads integrated into the avionics much easier. The OBC used the PowerPC MPC8548 processor, which run at 1GHz. Plug and play mechanism was adopted to make the OBC recognize the devices dynamically when they powered on, which accelerated the system integration; furthermore, the software modules were also allowed to install or uninstall dynamically on-line for flexibility. For the modular and various interfaces supported, payload modules such as GNSS-R receiver, ADS-B receiver and camera electronics was easily integrated into the avionics box, so the signaling were transferred via the backplane instead of cables.