PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Performance Analysis of a Particle-in-Cell Plasma Physics Code on Homogeneous and Heterogeneous HPC Systems

Abstract: PIC methods are one of the most used methods in plasma simulations. We present a comprehensible evaluation of the PIC code performance on four current parallel platforms: IBM PowerPC, Intel Nehalem (SMP), Intel Sandy Bridge (SMP) and ARM GPU. The behavior of computational algorithms and data structures are analyzed to deduce which code optimizations will make the best use of each platform.

Software Debugging Techniques for PowerPC 440 Processor Embedded Platforms

Abstract: GDB is a full featured symbolic software debugger. It can make certain tasks which are cumbersome to accomplish with XMD more streamlined. GDB can be used to debug software locally a local process running on the same machine and operating system as GDB itself, or remotely. In this document, GDB running on the local machine is used to connect to the GDB stub (also called GDB server) running within XMD. XMD automatically starts the GDB server after the user connects to the target processor.

Design of Video Codec Platform Based on PowerPC+WW602 Architecture

Abstract: In order to meet the needs of dual-channel high-resolution video encoding and decoding, as well as the need for long-term capture and recording of operating terminal screen information in important control scenarios such as shipborne, vehicle-mounted, and airborne, it is convenient for post-event technical analysis, service quality assessment, and exercises. Deduction and determination of responsibility for operation accidents. The hardware architecture of PowerPC+WW602 is researched, and a platform that supports dual-channel high-definition video encoding and decoding is designed and implemented. The compression algorithm of H.264 encoding standard is used to realize the encoding and decoding of video data, and advanced and mature technology is used to follow the generalization. The video codec platform design based on PowerPC+WW602 architecture can support single-channel or dual-channel video input of high-definition and standard-definition, and realize the codec transmission of two channels of video information. The delay of video capture and display is within 30ms, the picture is clear, and the video capture process is not lost.

Implementation of High-throughput PCIe based on FPGA and PowerPC

Abstract: This paper designed and implemented a direct memory access (DMA) architecture of PCI-Express (PCIe) between Xilinx field programmable gate array (FPGA) and Freescale PowerPC. The DMA architecture based on FPGA is compatible with the Xilinx PCIe core while the DMA architecture based on POWERPC is compatible with VxBus of VxWorks. The solutions provide a high-performance and low-occupancy alternative to commercial products. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, a novel strategy for the DMA engine is adopted, where the DMA register list is stored not only inside the FPGA during initialization phase but also in the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a VxWorks driver. The design is compatible with Xilinx FPGA Kintex Ultrascale Family, and operates with the Xilinx PCIe endpoint Generation 1 with lane configurations x8. A data throughput of more than 666 MBytes/s (memory write with data from FPGA to PowerPC) has been achieved with the single PCIe Gen1 x8 lanes endpoint of this design.

Single-event upset in advanced PowerPC microprocessors

Abstract: Proton and heavy-ion single-event upset susceptibility has been measured for the MotorolaPowerPC7400. The results show that this advanced device has low upset susceptibility, despite the scaling and design advances.