PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

An embedded control and monitor system for SAR using SOPC technology

Abstract: In the future, Synthetic Aperture Radar (SAR) requires enhanced capabilities, such as all-weather and better resolving power, more widely used in sciences, etc. New system to improve the control and monitor capability is desired by the development of the carrying-platform and SAR itself. A fast and small control and monitor system has been developed and tested. It employs SOPC (System On Programmable Chip) technology to satisfy the requirements of more advanced vehicle behavior in a small package, high-performance computing, and low power consumption, etc. The system presented in this paper is designed of Xilinx VirtexII p20 chip; a 1553B chip, an A/D chip has a SPI interface, etc. The project use PowerPC 405 embedded in V2P chip as a control computer to save PCB space, reduce total power consumption and enhance the computing capability of the system. This paper focuses on the design aspects of the hardware and the software of the system. Some experiments' results are given in this paper.

Embedded Linux operation system trimming customization method

Abstract: The invention discloses an embedded Linux operation system trimming customization method and belongs to the technical field of operation system trimming. The problems that an existing embedded Linux operation system code number based on a PowerPC hardware architecture is too large, the number of redundant modules is too large, and reading and modifying are not easy are solved. According to the technical scheme, an embedded Linux operation system based on the PowerPC hardware architecture is subjected to trimming and customization, the method comprises the steps that the embedded Linux operation system in the PowerPC hardware architecture is subjected to source code file level trimming; the embedded Linux operation system in the PowerPC hardware architecture is subjected to source code level trimming; source codes of the trimmed embedded Linux operation system are subjected to integral compiling, and embedded Linux operation system nucleus files are generated; and the compiled embedded Linux operation system nucleus files are used and are programmed into a storage of a main board in the PowerPC hardware architecture, then comprehensiveness testing is carried out, and whether the function or the performance of the trimmed embedded Linux operation system is normal is verified.

A framework for rapid development of dynamic binary translators

Abstract: Binary recompilation and translation play an important role in computer systems today. It is used by systems such as Java and .NET, and system emulators like VMWare and VirtualPC. A dynamic binary translator have several things in common with a regular compiler but as they usually have to translate code in real-time several constraints have to be made, especially when it comes to making code optimisations. Designing a dynamic recompiler is a complex process that involves repetitive tasks. Translation tables have to be constructed for the source architecture which contains the data necessary to translate each instruction into binary code that can be executed on the target architecture. This report presents a method that allows a developer to specify how the source and target architectures work using a set of scripting languages. The purpose of these languages is to relocate the repetitive tasks to computer software, so that they do not have to be performed manually by programmers. At the end of the report a simple benchmark is used to evaluate the performance of a basic IA32 emulator running on a PowerPC target that have been implemented using the system described here. The results of the benchmark is compared to the results of running the same benchmark on other, existing, emulators in order to show that the system presented here can compete with the existing methods used today. Several ongoing research projects are looking into ways of designing binary translators. Most of these projects focus on ways of optimising code in real-time and how to solve the problems related to binary translation, such as handling self-modifying code.

Design of User Define Instruction Set using APU

Abstract: This paper includes User Defined Instruction Decoding using the Auxiliary Processor Unit (APU) controller which allows the designer to extend the native PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric Coprocessor Module (FCM) which accelerate the system performance with the APU Controller, with an aim that Portions of certain software applications that are implemented in software can run faster by moving the implementation into hardware. In a VirtexTM-4 FX FPGA, the embedded PowerPCTM 405 (PPC405) processor can run software and offload computations to hardware modules in the FPGA. In such a system, a coprocessor interface known as the Auxiliary Processor Unit (APU) is used to transfer data between the processor and the FPGA. Because certain computations can be done more efficiently in software, and others in hardware, an APU-enhanced system results in a faster overall solution for many digital signal processing (DSP) applications. Index Terms – User define instruction, APU, FCM, Co-processor, embedded PowerPC etc.

A Novel Set of Directives for Multi-device Programming with OpenMP

Abstract: The latest versions of OpenMP have been offering support for offloading execution to the accelerator devices present in a variety of heterogeneous architectures via the target directives. However, these directives can only refer to one device at a time, which makes multi-device programming an explicit and tedious task. In this work, we present an extension of OpenMP in the form of a new set of directives (target spread directives) which offers direct support for multiple devices and allows the distribution of data and/or workload among them without explicit programming. This results in an additional level of parallelism between the host and the devices. The target spread directives were evaluated using the Somier micro-app in a PowerPC cluster node with up to four Nvidia Tesla V100 GPUs. The results showed a speedup of approximately 2X using four GPUs and the new directive set, in comparison with the baseline implementation which used one GPU and the existing target directive set.