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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
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Reference EntryDOI
16 Mar 2009
TL;DR: Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas but should be considered in light of their support for the RISC pipeline.
Abstract: Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline. Keywords: IBM 801; RISC; computer architecture; load/store architecture; instruction sets; pipelining; superscalar machines; superpipeline machines; optimizing compiler; branch and execute; delayed branch; cache; Harvard architecture; delayed load; superscalar; superpipelined
Patent
21 Jul 2017
TL;DR: In this article, the authors proposed a network message matching and receiving unit based on an FPGA. But the work in this paper is limited to the case where the data is transferred to a message capture module and an information return module after being completely parsed by a command parsing module.
Abstract: The invention discloses a network message matching and receiving unit based on an FPGA. An upper computer sends a command request of a user to the FPGA through PowerPc, and the data is transferred to a message capture module and an information return module after being completely parsed by a command parsing module; a message receiving module receives a message sent by network equipment under test through a network port and sends the received message to the message capture module; the message capture module matches the message received from the message receiving module according to a command transferred by the command parsing module, and sends the message that is correctly matched to a message storage module; and the information return module orderly returns the data that is received from the message storage module to the PowerPc according to the requirements of the command parsing module. The network message matching and receiving unit disclosed by the invention can realize the reception of the network port message, and is suitable for receiving the messages at rates of 1000Mbps, 100Mbps and 10Mbps.
Patent
20 Oct 2017
TL;DR: In this paper, a servo hydraulic energy measurement and control system based on a PowerPC and an FPGA is presented, which consists of a hardware part and a software part.
Abstract: The invention relates to a servo hydraulic energy measurement and control system based on a PowerPC and an FPGA. The system consists of a hardware part and a software part. The hardware part includes a power supply, a clock, a memory, an analog-digital integrated channel, a CPLD, a PowerPC, an FPGA, a flash memory, a UART, and an Ethernet PHY. The software part includes a drive, a board-level support package, an operating system, a file system, an IP data interface module, a control data interface module, a data acquisition monitoring module, a command analysis module, a command execution module, and a real-time status report module. The system can be connected via a network with a principal computer through Ethernet communication. The system can receive a control command from the principal computer, analyze the control command, and remotely and automatically control a servo hydraulic energy system through a peripheral digital-analog integrated circuit controlled by the FPGA. Moreover, the system can collect and receive the status parameters of the servo hydraulic energy system and feed back the status parameters to the principal computer for monitoring and using.
Patent
15 Mar 2006
TL;DR: In this article, a method for accelerating analog of power PC system structure by operating Linux internal core page table includes intercepting read / write operation of internal core Page table region and carrying out queen management for them for controlling internal page table read/ write carried out frequently to raise system cache hit rate for making up weakness of PPClinux.
Abstract: A method for accelerating analog of power PC system structure by operating Linux internal core page table includes intercepting read / write operation of internal core page table region and carrying out queen management for them for controlling internal core page table read / write carried out frequently to raise system cache hit rate for making up weakness of PPClinux to achieve high efficiency of simulation
Patent
10 Oct 2017
TL;DR: In this paper, a method for achieving self-adaption of a network interface in a mode of PowerPC DPAA is presented. But the method is applied in the DPAA mode of a PowerPC frame.
Abstract: The invention discloses a method for achieving self-adaption of a network interface in a mode of PowerPC DPAA. The method is applied in the DPAA mode of a PowerPC frame. The PowerPC hardware frame adopts a PowerPC multi-core network processor and the DPAA mode, and is allocated with a kilomega PHY chip. The method includes the steps of firstly obtaining current network status data; secondly allocating the read network status data to a relative register of the PowerPC network interface to achieve allocation of the interface mode, and finally achieving the self-adaption of the network interface. Compared with the prior art, the method for achieving the self-adaption of the network interface under the mode of PowerPC DPAA can achieve self-adaption of network interfaces, save system resources, achieve flexible arrangement, automatically complete allocation processes, and is high in allocation efficiency, high in practicability, wide in application range and easy to popularize.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823