PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

A 2.2 W, 80 MHz superscalar RISC microprocessor

Abstract: A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

The PowerPC Architecture: A Specification for a New Family of RISC Processors

Abstract: This is the official technical description of the PowerPC architecture and its hardware conventions, developed jointly by IBM, Motorola, and Apple. The book is an essential reference for hardware and system-software designers and applications programmers developing a range of products using implementations of the PowerPC family of microprocessors-from palmtops to teraFLOPS. The PowerPC architecture provides a stable base for software, allowing applications that run on one PowerPC processor to run consistently on any other PowerPC processor. In addition, well-designed operating systems can be moved from one processor implementation to another by making only a few minor changes. To achieve this, the specification of the architecture has been structured into three Books, corresponding to a distinct level of the architecture: Book I, User Instruction Set Architecture, describes the registers, instructions, storage model, and execution model that are available to all application programs. Book II, Virtual Environment Architecture, describes features of the architecture that permit application programs to create or modify code, to share data among programs in a multiprocessing system, and to optimize the performance of storage accesses. Book III, Operating Environment Architecture, describes features of the architecture that permit operating systems to allocate and manage storage, to handle errors encountered by application programs, to support I/O devices, and to provide the other services expected of secure, modern multiprocessor operating systems. An important feature of these specifications is that they only constrain implementations on matters that affect software compatibility. Even more significant, they specify the architecture in a manner that is independent of implementation. The PowerPC Architecture is a must for anyone who needs to understand the levels of compatibility between different processors in the PowerPC family-the 601 microprocessor, the 603 (low-end, battery-powered requirements), 604 (optimized price/performance for scaleable symmetric multiprocessors), and the 620 (for high-end technical and commercial requirements about performance).

Design and analysis of power distribution networks in PowerPC/sup TM/ microprocessors

Abstract: We present a methodology for the design and analysis of power grids in the PowerPC/sup TM/ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC/sup TM/ 750 microprocessor is presented.

Test program generation for functional verification of PowerPC processors in IBM

Abstract: A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon.

Mambo: a full system simulator for the PowerPC architecture

Abstract: Mambo is a full-system simulator for modeling PowerPC-based systems. It provides building blocks for creating simulators that range from purely functional to timing-accurate. Functional versions support fast emulation of individual PowerPC instructions and the devices necessary for executing operating systems. Timing-accurate versions add the ability to account for device timing delays, and support the modeling of the PowerPC processor microarchitecture. We describe our experience in implementing the simulator and its uses within IBM to model future systems, support early software development, and design new system software.