scispace - formally typeset
Search or ask a question
Topic

PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
More filters
Proceedings ArticleDOI
07 Feb 2000
TL;DR: This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS.
Abstract: This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS. Nominal processor clock frequency is 1.0 GHz. At the fast end of the process distribution the processor reaches 1.15 GHz (1.87 V, 101/spl deg/C, 112 W). As in a previous design, nearly the entire processor is implemented using delayed-reset and self-resetting dynamic circuit macros. New contributions include: (1) a fully pipelined, four execution-stage IEEE double-precision floating-point unit (FPU) with fused multiply-add. 2) Sum-addressed memory management units (MMUs) and 64 kB 2-cycle caches. (3) Support for the full 64 b PowerPC instruction set. (4) Dynamic PLA-based control. (5) A microarchitecture and floorplan that balances critical paths. (6) Delayed-reset dynamic circuits that support stress testing (burn-in). 7) Improved clock generation and distribution.

36 citations

Patent
10 Apr 1997
TL;DR: In this paper, a byte-lane swapping logic is added to the inbound and outbound I/O data paths for transferring data between system components in the appropriate Endian format.
Abstract: To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.

35 citations

Proceedings ArticleDOI
C. Hunter1, J. Slaton1, J. Eno1, R. Jessani1, C. Dietz2 
02 Oct 1994
TL;DR: The RAM BIST design implemented on the PowerPC 603 microprocessor encompasses a novel state machine design built using logic synthesis tools and is constrained by the need to minimize area overhead while providing high test coverage and rapid at-speed testing.
Abstract: The PowerPC 603 microprocessor is designed for low power, low cost computing applications. A RAM built-in-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays. The design is constrained by the need to minimize area overhead while providing high test coverage and rapid at-speed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessor.

35 citations

24 Sep 2004
TL;DR: The Purdue Software Receiver (PSR) as mentioned in this paper is a real-time software defined GPS receiver developed at Purdue University for research and teaching purposes, which is designed to maximize reusability of the code.
Abstract: The Purdue Software Receiver (PSR) is a real-time software defined GPS receiver developed at Purdue University for research and teaching purposes. The receiver’s software architecture was designed to maximize reusability of the code. This includes employing the receiver in a non real-time mode as a postprocessing tool for sampled GPS data as well as a realtime mode operating from an antenna and digital receiver card. Real-time operation is enabled by single instruction multiple data (SIMD) instructions found on modern x86 and PowerPC processors. The PSR is coded in C++, making use of threaded objects to encapsulate functions and related data together and to reduce unnecessary copying of data. A software construct termed the “pipewall” is used to separate the low level (correlation and tracking) functions from the higher level navigation processing. A short description of a laboratory GPS signal recording system will also be presented.

35 citations

Proceedings ArticleDOI
04 Jun 2005
TL;DR: A modular development framework that can be adapted for different systems by simply changing the software or firmware parts, based on the demands of the system to be developed.
Abstract: System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, HTTP, Java, and Lab View for control and communication, together with the MicroC/OS-II and OSE operating systems

35 citations


Network Information
Related Topics (5)
Scalability
50.9K papers, 931.6K citations
77% related
CMOS
81.3K papers, 1.1M citations
77% related
Software
130.5K papers, 2M citations
77% related
Integrated circuit
82.7K papers, 1M citations
76% related
Cache
59.1K papers, 976.6K citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823