PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

POWER and PowerPC

Abstract: Foreword Preface 1 Modern Computer Design Concepts 1.1 Introduction 1.2 RISC Architectures 1.3 An Introduction to Pipelining 1.4 Beyond Simple Pipelines 1.5 Instruction Scheduling 1.6 Modern Computer Systems 1.7 POWER and PowerPC: The Big Picture 1.8 The Rest of the Book 1.9 References 2 POWER Architecture 2.1 Introduction 2.2 Instruction Set Basics 2.3 Fixed-Point Unit 2.4 Branch Unit 2.5 Floating-Point Unit 2.6 Virtual Address Generation and Translation 2.7 Protection 2.8 References 3 POWER1 Implementation: Pipelines 3.1 Introduction 3.2 Pipelined Structure of the CPU 3.3 Branch Unit 3.4 Fixed-Point Unit 3.5 Floating-Point Unit 3.6 References 4 POWER1 Implementation 4.1 Introduction 4.2 Solving the Branch Problems 4.3 Branches in the POWER1 4.4 Precise Interrupts 4.5 Interrupts in POWER1 4.6 References 5 POWER1 Implementation: Cache Memories 5.1 Introduction 5.2 Cache Memory Overview 5.3 POWER1 Instruction Cache 5.4 POWER1 Data Cache 5.5 References 6 POWER2: The Next Generation 6.1 Introduction 6.2 POWER Architecture Extensions 6.3 Pipeline Overview 6.4 Branch Unit 6.5 Fixed-Point Unit 6.6 Floating-Point Unit 6.7 Instruction Cache 6.8 Data Cache 6.9 Summary 6.10 References 7 PowerPC Architecture 7.1 Introduction 7.2 Fixed-Point Unit 7.3 Branch Unit 7.4 Floating-Point Unit 7.5 Virtual Address Generation and Translation 7.6 PowerPC versus POWER: Simplification 7.7 PowerPC versus POWER: Extensions 7.8 Summary and Conclusions 7.9 References 8 PowerPC 601 Implementation 8.1 Introduction 8.2 Pipelines 8.3 Branch Processing 8.4 Cache Memory 8.5 PowerPC 601 and POWER1 Implementations 8.6 Summary and Conclusions 8.7 References 9 PowerPC: Support for Multiprocessing 9.1 Introduction 9.2 Architectural Support for Multiprocessing 9.3 Memory Ordering 9.4 Cache Coherence 9.5 Higher-Level Caches 9.6 Cache and Lookaside Buffer Management 9.7 References 10 System Organization 10.1 Introduction 10.2 PowerPC Personal Computers 10.3 PowerPC Multiprocessor Systems 10.4 RS/6000 Workstation Overview 10.5 RS/6000 Main memory 10.6 RS/6000 Input/Output System 10.7 RS/6000 Clustered Multicomputers 10.8 Summary 10.9 References 11 PowerPC 601 and Alpha 21064 11.1 Introduction 11.2 Implementation Overview 11.3 Architecture Comparison 11.4 Summary 11.5 References A IEEE 754 Floating-Point Standard A.1 Floating-Point Numbers A.2 Floating-Point Exceptions B POWER Instruction Format C POWER Instruction Set Sorted by Mnemonic D PowerPC Instruction Formats E PowerPC Instruction Set Sorted by Mnemonic F Cross Reference for Changed POWER Mnemonics Bibliography Index

A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration

Abstract: A multilayer run-time reconfiguration architecture (MRRA) is developed for autonomous run-time partial reconfiguration of field-programmable gate-array (FPGA) devices. MRRA operations are partitioned into logic, translation, and reconfiguration layers along with a standardized set of application programming interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. In particular, FPGA configurations can be manipulated at runtime using on-chip resources. A corresponding logic control flow is developed for a prototype MRRA system on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Evaluations of these prototypes on a number of benchmark and hashing algorithm case studies indicate the enhanced resource utilization and run time performance of the developed approaches.

Approximation of Worst-Case Execution Time for preemptive multitasking systems

Abstract: The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and subsequently limits a task's execution time during operation. If a task exceeds the WCET, this situation is detected and either a handler is invoked or control is transferred to a human operator. Such control systems usually support preemptive multitasking, and if an object-oriented programming language (e.g., Java, C++, Oberon) is used, then the system may also provide dynamic loading and unloading of software components (modules). Only modern, state-of-the art microprocessors can provide the necessary compute cycles, but this combination of features (preemption, dynamic unloading of modules, advanced processors) creates unique challenges when estimating the WCET. Preemption makes it difficult to take the state of the caches and pipelines into account when determining the WCET, yet for modem processors, a WCET based on worst-case assumptions about caches and pipelines is too large to be useful, especially for big and complex real-time products. Since modules can be loaded and unloaded, each task must be analyzed in isolation, without explicit reference to other tasks that may execute concurrently. To obtain a realistic estimate of a task's execution time, we use static analysis of the source code combined with information about the task's runtime behavior. Runtime information is gathered by the performance monitor that is included in the processor's hardware implementation. Our predictor is able to compute a good estimation of the WCET even for complex tasks that contain a lot of dynamic cache usage, and its requirements are met by today's performance monitoring hardware. The paper includes data to evaluate the effectiveness of the proposed technique for a number of robotics control kernels that are written in an object-oriented programming language and execute on a PowerPC 604e-based system.

Constraint satisfaction for test program generation

Abstract: A central problem in automatic test generation is solving constraints for memory access generation. A framework, and an algorithm that has been implemented in the Model-Based Test-Generator are described. This generic algorithm allows flexibility in modeling new addressing modes with which memory accesses are generated. The algorithm currently handles address constraint satisfaction for complex addressing modes in the PowerPC, x86, and other architectures. >

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture

Abstract: Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on the Intel® Architecture (IA) ISA, a lot of attention has been given to translating IA to other ISAs. The recent trends in industry for both smaller ultra-mobile PCs and more powerful embedded and mobile internet devices (e.g. smartphones) are blurring the frontiers between these distinct markets. As a result, this market convergence is creating great interest in DBT from ISAs that currently dominate the embedded and mobile-internet-device markets (e.g. ARM, MIPS, and PowerPC) to IA. This paper investigates the main challenges that arise when targeting IA in a DBT. We identify the two key issues in efficiently translating from other ISAs to IA: IA's small number of registers, and its condition-code handling mechanism. To address these issues, we propose a combination of software and hardware solutions. Although motivated by IA, these techniques are not IA-specific, and they can be applied to other architectures with similar limitations to make them better DBT-targets. We have prototyped these techniques in Harmonia, an ARM-to-IA DBT tool based on open-source QEMU. Our experiments show that Harmonia achieves an average of 55% (up to 164%) of the performance of highly optimized native binaries, and an average speedup of 2.2 x on top of the baseline QEMU.