scispace - formally typeset
Search or ask a question
Topic

PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
More filters
Proceedings ArticleDOI
18 Jun 2000
TL;DR: A new parallel algorithm for CRC generation and its software as well as hardware implementation is described, which yields an unlimited speed-up potential over the bit-wise serial algorithm.
Abstract: Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. A new parallel algorithm for CRC generation and its software as well as hardware implementation is described. For the software implementation, this paper has focused on the 32-bit CRC used in the Ethernet, computed on a general purpose PowerPC microprocessor with the new AltiVec technology. A speedup by a factor of 4.57 over the standard table-lookup algorithm was obtained. A hardware implementation of the algorithm is then discussed, which yields an unlimited speed-up potential over the bit-wise serial algorithm.

25 citations

Proceedings ArticleDOI
03 Oct 2000
TL;DR: A new method for measuring both peak-to-peak and RMS jitter in PLL output signals and its theoretical basis is derived from analytic signal theory.
Abstract: This paper demonstrates a new method for measuring both peak-to-peak and RMS jitter in PLL output signals. The theoretical basis for this method is derived from analytic signal theory. To validate the method, experimental data from PowerPC/sup TM/ microprocessor jitter measurements is compared with results obtained with the conventional time interval analyzer (TIA) technique.

25 citations

Journal ArticleDOI
TL;DR: This work focuses on tool design for the development of microarchitectures, which implement the instruction set, and the FMW PowerPC-based simulation tool will help designers accurately evaluate the effectiveness and validate the correctness of new microprocessor mechanisms.
Abstract: Microprocessor designers use multiple simulation tools with varying degrees of modeling details ranging from the instruction set of the microprocessor to the circuit implementation. We focus on tool design for the development of microarchitectures, which implement the instruction set. Microarchitecture design involves both functional and performance simulators. A functional simulator models a machine's architecture, or instruction set, with functional correctness. A performance simulator models the machine organization, or microarchitecture, and is concerned with machine performance. Sometimes these performance simulators are also referred to as cycle-accurate simulators to reflect their concern with timing issues. The FMW PowerPC-based simulation tool will help designers accurately evaluate the effectiveness and validate the correctness of new microprocessor mechanisms.

25 citations

Proceedings ArticleDOI
10 Oct 2008
TL;DR: A method that permits to quickly estimate the power consumption at the first steps of a systempsilas design and its use at different levels in the component based AADL design flow is presented.
Abstract: This paper presents a method that permits to quickly estimate the power consumption at the first steps of a systempsilas design. We present multi-level power models and show how to use them at different levels of the specification refinement in the component based AADL design flow. PET, a power estimation tool, is being developed in the frame of the European SPICES project. It first prototype gives, in the case of a processor binding, power consumption estimations, for software components in the AADL component assembly model, with a maximal error ranging roughly from 5% to 30% depending on the refinement level. We illustrate our approach with the power model of the PowerPC 405, and its use at different levels in the AADL flow.

24 citations

Proceedings ArticleDOI
17 Oct 2010
TL;DR: Heterogeneous multi-core processors, such as the IBM Cell processor, are presented, and an implementation of the Java Virtual Machine which operates over the Cell processor is presented, thereby making this platforms more readily accessible to mainstream developers.
Abstract: Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores support different instruction set architectures, and the processor as a whole does not provide coherence between the different cores' local memories.We present Hera-JVM, an implementation of the Java Virtual Machine which operates over the Cell processor, thereby making this platforms more readily accessible to mainstream developers. Hera-JVM supports the full Java language; threads from an unmodified Java application can be simultaneously executed on both the main PowerPC-based core and on the additional SPE accelerator cores. Migration of threads between these cores is transparent from the point of view of the application, requiring no modification to Java source code or bytecode. Hera-JVM supports the existing Java Memory Model, even though the underlying hardware does not provide cache coherence between the different core types.We examine Hera-JVM's performance under a series of real-world Java benchmarks from the SpecJVM, Java Grande and Dacapo benchmark suites. These benchmarks show a wide variation in relative performance on the different core types of the Cell processor, depending upon the nature of their workload. Execution of these benchmarks on Hera-JVM can achieve speedups of up to 2.25x by using one of the Cell processor's SPE accelerator cores, compared to execution on the main PowerPC-based core. When all six SPE cores are exploited, parallel workloads can achieve speedups of up to 13x compared to execution on the single PowerPC core.

24 citations


Network Information
Related Topics (5)
Scalability
50.9K papers, 931.6K citations
77% related
CMOS
81.3K papers, 1.1M citations
77% related
Software
130.5K papers, 2M citations
77% related
Integrated circuit
82.7K papers, 1M citations
76% related
Cache
59.1K papers, 976.6K citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823