PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Durable memory RS/6000 system design

Abstract: The DM/6000 prototype is a fault-tolerant/durable-memory RS/6000. The main storage of this system is battery backed so as to maintain memory content across prolonged power interruptions. In addition, there are no single points of failure, and all likely multiple failure scenarios are covered. The prototype is intended to match the data integrity and availability characteristics of RAID5 disks. Redundancy is managed in hardware and in transparent to the software; application programs and the operating system (AIX) can run unmodified. The prototype is based on the IBM PowerPC 601 microprocessor operating at 80 MHz and is equivalent in performance and software appearance to a conventional 4-way shared bus, cache coherent, symmetric multiprocessor (SMP), with 4 gigabytes of non-volatile main storage. >

Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA

Abstract: Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entirely hardware-based in order to increase the speed of the circuit evaluation which uses a large training set (360 images/23040 bytes). The fitness evaluation time for 1000 generations consisting of 16 individuals is 623 ms, twice as fast as software fitness evaluation performed on a workstation running at a 30 times higher clock frequency. The rest of the genetic algorithm (GA) runs in software on a PowerPC 405 processor core on the FPGA. The total evolution time for 1000 generations is 1313 ms, equivalent to the total time used by the workstation. Resource utilization for the fitness evaluation module is 1393 slices (10%) of a XC2VP30 device.

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Abstract: Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.

Enhanced compression techniques to simplify program decompression and execution

Abstract: Compressing instruction sequences can reduce the cost of embedded systems by reducing program ROM-size requirements. Compression also facilitates the use of RISC core architectures, like the PowerPC/sup TM/ architecture, in embedded systems. Compression techniques are presented which enable decompression and execution of compressed code to occur without the need of a lookaside table (LAT) or cache lookaside buffer (CLB). These techniques successfully merge code modification and compression into a single software preprocessing step. Decompression and execution of compressed code are made very simple. An application of these techniques to about 120000 instructions of PowerPC firmware code is described.

A programmer's view of performance monitoring in the PowerPC microprocessor

Abstract: Performance monitor (PM) support in on-chip PowerPC® microprocessors is used to analyze processor, software, and system attributes for a variety of workloads. The interface to the PowerPC 604® microprocessor, which we abbreviate “604,” has been externalized to end users. We discuss the enhanced PM support available in an upgrade of the 604, the PowerPC 604e™ microprocessor, which we abbreviate “604e.” We discuss the challenges related to the externalization of the PM support as it relates to other PowerPC processors not derived from the 604 and briefly contrast these PMs with other PMs. We also describe an application programming interface (API) to the on-chip PM support, its design methodology, and its usage considerations, intended to meet these challenges.