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PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.


Papers
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Book ChapterDOI
20 Aug 2009
TL;DR: This paper reports on a case study, which is believed to be the first to produce a formally verified end-to-end implementation of a functional programming language running on commercial processors.
Abstract: This paper reports on a case study, which we believe is the first to produce a formally verified end-to-end implementation of a functional programming language running on commercial processors. Interpreters for the core of McCarthy's LISP 1.5 were implemented in ARM, x86 and PowerPC machine code, and proved to correctly parse, evaluate and print LISP s-expressions. The proof of evaluation required working on top of verified implementations of memory allocation and garbage collection. All proofs are mechanised in the HOL4 theorem prover.

21 citations

Proceedings ArticleDOI
12 Jan 1997
TL;DR: Virtual Memory MTU Reassembly (VMMR) allows hardware/software interfaces to efficiently DMA large MTUs in hardware pages and remap them to a contiguous address space and can outperform memcopy by one to two orders of magnitude.
Abstract: Message transfer unit (MTU) reassembly schemes in modern operating systems cause I/O performance degradation when MTU sizes are larger than the architecture's page size. This can happen with emerging network technologies, such as Asynchronous Transfer Mode (ATM), where MTUs can be 64 KB or greater Traditional solutions either reassemble using memory copy or preallocate contiguous memory; these, however lack speed or consume excess resources, respectively. This paper presents an alternative scheme called Virtual Memory MTU Reassembly (VMMR) which reassembles non-contiguous pages through virtual memory remapping. VMMR allows hardware/software interfaces to efficiently DMA large MTUs in hardware pages and remap them to a contiguous address space. Studies done on a PowerPC 601 show that this method can outperform memcopy by one to two orders of magnitude (the maximum VMMR bandwidth is 14.7 Gbits/sec). High-performance multimedia applications, such as video on demand and video conferencing, can greatly benefit from such a performance boost.

20 citations

Journal ArticleDOI
TL;DR: Using the best tools and methodoiogy available, the design team took the 603 from concept to working silicon in 18 months, providing fully functional first-pass silicon that ran at the design target speed of BOMHz.
Abstract: Following closely on the heels of its predecessor, the PowerPC 601 microprocessor [ 11, the 603 microprocessor was developed at the joint Motorola/ IBM/Apple Somerset Design Center in Austin, Texas. The 603 microarchitecture evolved from Apple, IBM, and Motorola’s collective experience on several past designs. The similarity of the POWER and PowerPC architectures permitted the use of sample traces generated by RISC System/6000 machines for evaluation of design trade-offs. The compiler groups also provided their insight to ensure the traces from the past generation of processors and compilers, with their own specific peculiarities, did not misguide the 603’s microarchitecture definition, and that tradeoffs selected were appropriate for the next generation of compilers. To accelerate the design and test process, engineers employed a formal VLSI desigrl mrthodolugy derived from the best ofboth IBM and Motorola’s CAD tools. These tools enable both the rapid design and dense packing capability necessary to produce very high-volume, high-yield microprocessors for the commercial market. The 603 design team employed a combination of custom circuitry (for arrays), library components (for data paths), and standard cell place and route (for random logic) to accomplish the 603 design. Using the best tools and methodoiogy available, the design team took the 603 from concept to working silicon in 18 months. Ongoing design evaluation and debugging, including simulation of 28 billion processor cycles prior to tape-out, provided fully functional first-pass silicon that ran at the design target speed of BOMHz. The PowerPC 603 microprocessor is manufactured by Motorola in Ausrm,Texas, and by IBM in Burlingron, Vt. Motorola and IBM both fabricate the 603 using a 0.5pm, 4.level metal, 3.3VDC CMOS process with design rules compatible with both companies’ semiconductor processes. The die is designed to be packaged in either a 240-pin ceramic quad flat pack or a ball-grid array package. Figure 1 is a photograph of the 603 die.

20 citations

Journal ArticleDOI
01 Apr 2014
TL;DR: A complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm, which allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots.
Abstract: We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. Aside from image analysis, the module embeds a Linux distribution that allows to run programs specifically tailored for particular applications. The module is based on a Virtex-5 FXT FPGA which features powerful configurable logic and an embedded PowerPC processor. We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm's most computationally expensive process, the interest point detection. The module's overall performance is evaluated and compared to CPU and GPU-based solutions. Results show that the embedded module achieves comparable distinctiveness to the SURF software implementation running in a standard CPU while being faster and consuming significantly less power and space. Thus, it allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots.

20 citations

Book ChapterDOI
06 Nov 1996
TL;DR: A formal framework for the new process is described, the obstacles that are encountered in the modeling phase, and how to overcome them are identified, and the method was studied on an enhanced PowerPC processor.
Abstract: We address the problem of verification of implementations of complex processors using architectural level automatic test program generators A number of automatic test program generators exist, and are widely used for verification of the compliance of complex processors with their architectures We define a four stage verification process: (1) describing the processor implementation control as a Finite State Machine (2) deriving transition coverage on the FSM using methods from formal verification (3) translation of the covering tours to constraints on test programs (4) generation of test programs for each set of constraints This process combines a high quality and well defined theoretical method along with tools used in industrial practice There are a number of advantages of our Method: (a) The last three stages are automated (b) Implementing the FSM model involves relatively little expert designers time (c) The method is feasible for modem superscalar processors and was studied on an enhanced PowerPC processor We describe a formal framework for the new process, identify the obstacles that are encountered in the modeling phase, and show how to overcome them

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20232
20226
20215
20208
201916
201823