Topic
PowerPC
About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.
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19 Jun 2010
TL;DR: ISAMAP, a flexible instruction mapping driven by dynamic binary translation, provides a fast translation between ISAs, under an easy-to-use description, and is capable of translating 32-bit PowerPC code to 32- bit x86 and to perform local optimizations on the resulting x86 code.
Abstract: Dynamic Binary Translation (DBT) techniques have been largely used in the migration of legacy code and in the transparent execution of programs across different architectures. They have also been used in dynamic optimizing compilers, to collect runtime information so as to improve code quality. In many cases, DBT translation mechanism misses important low-level mapping opportunities available at the source/target ISAs. Hot code performance has been shown to be central to the overall program performance, as different instruction mappings can account for high performance gains. Hence, DBT techniques that provide efficient instruction mapping at the ISA level has the potential to considerably improve performance. This paper proposes ISAMAP, a flexible instruction mapping driven by dynamic binary translation. Its mapping mechanism, provides a fast translation between ISAs, under an easy-to-use description. At its current state, ISAMAP is capable of translating 32-bit PowerPC code to 32-bit x86 and to perform local optimizations on the resulting x86 code. Our experimental results show that ISAMAP is capable of executing PowerPC code on an x86 host faster than the processor emulator QEMU, achieving speedups of up to 3.16x for SPEC CPU2000 programs.
13 citations
TL;DR: In this paper, the failure data are plotted using Weibull distributions. Failure mechanisms for both CQFP and CBGA packages were presented and failure criteria for both packaging technologies were also presented.
Abstract: Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and chip inputs/outputs (I/Os). This trend has placed increased emphasis on microelectronics packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count gets higher, the pitch has been driven smaller to the point where other solutions also become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce printed-circuit board real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 40 mm (304 I/Os) CQFPs are being utilized. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test setup, and solder joint failure criteria. Failure mechanisms for both packaging technologies will also be presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100/spl deg/C and -40 to 125/spl deg/C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessors computer environments. To predict solder joint reliability of surface-mount technology, a key parameter is: the temperature rise above ambient at the solder joint, /spl Delta/T. In-situ field temperature measurements were taken for a range of computer platforms in an office environment, at the central-processing units. Printed-circuit boards (PCB) were not uniform, therefore only maximum temperature regions of the board were measured. These maximum temperatures revealed the mean to be less than 20/spl deg/C above ambient (i.e., /spl Delta/T<20/spl deg/C) regardless of the power of the device. The largest /spl Delta/T measured in any system was less than 30/spl deg/C above ambient. These temperature measurements of actual computer systems are in close agreement with IPC-SM-785. By utilizing the measured PCB temperature rise, solder joint fatigue life was calculated for the 21 mm ceramic ball-aid-array (CBGA), the package for the PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors. The average on-off /spl Delta/T for most computer applications is approximately 20/spl deg/C. For an average on-off /spl Delta/T of 30/spl deg/C, the 21 mm CBGA has an estimated fatigue life of over 25 years while the 32 mm and 40 mm CQFP's have an estimated fatigue life of over 50 years.
13 citations
10 May 2009
TL;DR: An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESIII and a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments.
Abstract: An ATCA-based computation platform for data acquisition and trigger(TDAQ) applications has been developed for multiple future projects such as PANDA, HADES, and BESIII. Each Compute Node (CN) appears as one of the fourteen Field Replaceable Units (FRU) in an ATCA shelf, which in total features a high performance of 1890 Gbps inter-FPGA onboard channels, 1456 Gbps inter-board backplane connections, 728 Gbps full-duplex optical links, 70 Gbps Ethernet, 140 GBytes DDR2 SDRAM, and all computing resources of 70 Xilinx Virtex-4 FX60 FPGAs. Corresponding to the system architecture, a hardware/software co-design approach is proposed to ease and accelerate the development for different experiments. In the uniform system design, application-specific computation is to be implemented as customized hardware co-processors, while the embedded PowerPC processor takes charge of flexible slow controls and transmission protocol processing.
13 citations
08 Mar 2004
TL;DR: This work aims at reducing the overhead for cooperative multithreading context switches at compile time by using standard compiler techniques such as context-insensitive analysis and register usage is rearranged to reduce the amount of context-switch code.
Abstract: Multithreading is an efficient way to improve efficiency of processor cores in embedded products for networking infrastructures. To make such improvements also accessible to processor cores without hardware support for multithreading, we present a concept for efficient software multithreading through compiler post-pass optimization of the application code. Our approach aims at reducing the overhead for cooperative multithreading context switches at compile time by using standard compiler techniques such as context-insensitive analysis. Additionally, register usage is rearranged to reduce the amount of context-switch code by exploiting multiple-load/store instructions. Performance model analysis encourages the use of software multithreading to improve processor utilization by showing the benefit of our approach. We present results obtained by an implementation for the PowerPC ISA (Instruction Set Architecture) using the code of a real network application (iSCSI). We were able to reduce the expected run-time of a context switch to as little as 38% of the original.
13 citations