PowerPC

About: PowerPC is a research topic. Over the lifetime, 1184 publications have been published within this topic receiving 22297 citations. The topic is also known as: ppc.

Speculatively vectorized bytecode

Abstract: Diversity is a confirmed trend of computing systems, which present a complex and moving target to software developers. Virtual machines and just-in-time compilers have been proposed to mitigate the complexity of these systems. They do so by offering a single and stable abstract machine model thereby hiding architectural details from programmers.SIMD capabilities are common among current and expected computing systems. Efficient exploitation of SIMD instructions has become crucial for the performance of many applications. Existing auto-vectorizers operate within traditional static optimizing compilers, and use details about the target architecture when generating SIMD instructions. Unfortunately, auto-vectorizers are currently too complex to be included in a constrained Just-In-Time (JIT) environment.In this paper we propose Vapor SIMD: a speculative approach for effective just-in-time vectorization. Vapor SIMD first applies complex ahead-of-time techniques to vectorize source code and produce bytecode of a standard portable format. Advanced JIT compilers can then quickly tailor this bytecode to exploit SIMD capabilities of appropriate platforms, yielding up to 14.7x and 11.8x speedups on x86 and PowerPC platforms (including JIT-compilation time). JIT compilers can also seamlessly revert to non-vector code, in the absence of SIMD capabilities or in the case of a third-party non-vectorizing JIT compiler, yielding 93% or more of the original performance.

Media processing with field-programmable gate arrays on a microprocessor's local bus

Abstract: The Chidi system is a PCI-bus media processor card which performs its processing tasks on a large field-programmable gate array (Altera 10K100) in conjunction with a general purpose CPU (PowerPC 604e). Special address-generation and buffering logic (also implemented on FPGAs) allows the reconfigurable processor to share a local bus with the CPU, turning burst accesses to memory into continuous streams and converting between the memory's 64-bit words and the media data types. In this paper we present the design requirements for the Chidi system, describe the hardware architecture, and discuss the software model for its use in media processing.

A modular approach to Motorola PowerPC compilers

Abstract: The need for balancehetween software and hardware is a well-known principle of RISC microprocessor design methodologies. In order to achieve a high level of performance, RISC microprocessors are designed to allow compilers to take full advantage of the pipelines and resources available. The PowerPC family of microprocessors is being designed to he used for many purposes, ranging from low-power embedded controllers to powerful, supercomputerclass multiprocessor systems. This diversity of uses will lead to an equally diverse set of operating system environments, including AIX, Macintosh OS, Solaris and Windows/NT, among others. Despite the multitude of PowerPC processor and system configurations being developed, there remains a need for highly optimizing compilers that utilize both the base PowerPC Architecture as well as other implementations of the chips and systems designed around the architecture. Motorola has developed a highly optimizing, modular compilation environment that can be quickly adapted to various PowerPC microprocessor and system configurations. This suite of C, C++ and Fortran compilers is designed to meet the following criteria: l Highly optimizing, ensuring opri-mal performance for PowerPC microprocessors l Highly retargetable, ensuring rapid time-to-market l Highly configurable, supporting multiple object file and debugging formats l Compliant to software standards, ensuring portability of code between chips This article will describe the modular structure of the compiler, the data and information flow through the major phases of the compiler, and offer some discussion on architecture and implementation-specific optimizations currently performed in the PowerPC compilers. Through examples and descriptions, an understanding can be achieved as to how the Motorola PowerPC compilers are designed to provide the high performance and diversity that is essential to the PowerPC Architectwe. The Motorola compilation system, based partially on technology acquired from Apogee Software for the 88000 architecture, consists of a series of components that collectively =a \" provide highly optimized PowerPC microprocessor code for a wide range of source languages, object file and debugging formats, and system environments. Conceptually, the heart of the Motorola compilation system is a common core that integrates multiple front ends with target-specific code generators to provide consistently high performance across an extremely wide range of target environments (see

Application migration from linux prototype to deployable ima platform using arinc 653 and open gl

Abstract: Linux offers a low cost, rapid-prototyping capability for integrated modular avionics (IMA) applications, but moving these prototypes to a deploy able ARINC 653 partitioned system presents many challenges to a developer. This paper discusses the steps needed to migrate an OpenGL-based graphic application from a Linux prototype to a working ARINC 653 IMA platform. It makes use of Wind River's VxWorks 653 operating systems utilizing Seaweed software's certifiable OpenGL product. An example will be discussed of this software running on VxWorks 653 using PowerPC hardware with a Radstone PMC graphics adapter.

WARP, a Modular Testbed for Configurable Wireless Network Research at Rice

Abstract: Wireless Open-Access Research Platform (WARP), developed at CMC lab, Rice University, provides a scalable and configurable platform for wireless network research. Its programmability and flexibility makes it easy to prototype and implement various physical and network layer protocols and standards. In order to share algorithms and implementations developed at different research centers, an online open-access repository is used so that wireless network researchers can collaborate to initiate multi-disciplinary system designs. I. WARP PLATFORM ARCHITECTURE Rice University’s WARP [1, 2] is a scalable, extensible and programmable wireless platform, built from the ground up, to prototype wireless networks. The platform architecture consists of four key components: custom hardware, platform support packages, openaccess repository and research applications; all together providing a reconfigurable wireless testbed for students and faculty. Figure 1 shows the WARP boards in CMC lab. Fig. 1. WARP boards in the CMC lab. Custom Baseband Hardware: The WARP board is built up around Xilinx Virtex-II Pro FPGA as the primary communication processor, which along with the PowerPC processors embedded in the FPGA, provide a complete embedded programming environment for physical, medium access control (MAC) and network layer design. The dedicated multi-gigabit transceivers (MGTs) provide high speed board-to-board connections which make the WARP platform scalable and extendable. Moreover, four daughtercard slots on the WARP board can be used to connect the FPGA to the radio boards designed fully by Rice University students so that up to a 4× 4 multipleinput multiple-output (MIMO) system can be built. Using these radio boards, the testbed may be used for wideband wireless communications in the 2.4 GHz/5 GHz ISM/UNII bands. The radio link, designed for MIMO applications, guarantees the phase coherency of carriers by sharing a reference clock. Development Tools: The Xilinx ”Platform Studio” tool is an integrated programming environment that is used to control both the physical layer and MAC layer implementations. For physical layer design, Xilinx ”System Generator” , integrated in MATLAB Simulink, provides abstractions for building and debugging highperformance DSP systems in MATLAB/Simulink using the Xilinx Blockset. Moreover, the WARP board supports Simulink ”hardware co-simulation” that expedites the simulation and debugging steps. For MAC and network layer design, the WARP platform supports ”C” based applications on the PowerPC while interfacing the physical layer implementations in the FPGA fabric. Online Open-Access Repository: The open-access repository [3], accessible from the Internet, is the central archive for all source codes, models, platform support packages, application building blocks, research applications, design documents and hardware design files associated with WARP. The contents of the repository are verified by the project administrator at Rice University. II. WIRELESS NETWORK RESEARCH IMPACT WARP provides a unique platform to develop, implement and test advanced wireless algorithms. All the design files are shared and documented through the online open-access repository [3]. A major benefit of custom physical and MAC layer designs is that they facilitate multi-layer system design by providing a flexible framework for researchers with expertise in a specific layer and little background in other layers to implement advanced protocols while abstracting away other layers. The embedded PowerPC core in the Xilinx FPGA has been programmed using the C language to implement a flexible medium access development framework. This framework is in fact a set of software routines that can be used by network researchers to develop various advanced MAC and networking protocols while abstracting away the physical layer. Using this framework, various wireless networks, e.g. ad-hoc and multi-hop networks, as well as cooperative communication systems, e.g. relay networks, can be implemented on multiple WARP boards. Furthermore, a 2× 2 MIMO OFDM physical layer transceiver, i.e. two daughtercard radio boards for each WARP node, has been designed and implemented on the WARP hardware. The data streams are spatially multiplexed on both the antennas. In order to up-convert the baseband signals to the RF band, two daughtercard radio boards are used in each WARP node. Error correcting codes, e.g. LDPC, have also been developed to fit in the WARP framework, and further enhance the wireless link performance. III. ACKNOWLEDGEMENT This work was supported in part by Nokia Corporation, Xilinx Inc., and by NSF under grants EIA-0321266, CCF-0541363, CNS0551692, and CNS-0619767.